8.1 Time Division Multiplexed Left Justified (TDMLJ) is not functional in Client mode

When the clock is enabled during a high level of the frame synchro signal (I2SMCC_WS) by writing I2SMCC_CR.CKEN = 1, the data alignment is incorrect.

Work Around

None.

Affected Device Revisions

A0A0-D1GA0-D2GA1A1-D1GA1-D2G
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