3 Pin Allocation Tables

Table 3-1. 14-Pin Allocation Table
I/O	14-Pin SOIC/TSSOP	A/D	Reference	Timers	16-Bit PWM/CCP	CWG	CLC	SPI	I²C	I3C®	UART	IOC	Interrupts	Basic
RA0	13	ANA0	—	—	—	—	—	—	—	—	—	IOCA0	—	ICDDAT ICSPDAT
RA1	12	ANA1	VREF+ (ADC)	TUIN0⁽¹⁾	—	—	—	—	—	—	—	IOCA1	—	ICDCLK ICSPCLK
RA2	11	ANA2	VREF- (ADC)	T0CKI⁽¹⁾	—	CWG1IN⁽¹⁾	—	—	—	—	—	IOCA2	INT0⁽¹⁾	—
RA3	4	—	—	—	—	—	—	—	—	—	—	IOCA3	—	MCLR V_PP
RA4	3	ANA4	—	T1G⁽¹⁾	—	—	—	—	—	—	—	IOCA4	INT1⁽¹⁾	CLKOUT SOSCO OSC2
RA5	2	ANA5	—	T1CKI⁽¹⁾ T2IN⁽¹⁾	PWM1ERS⁽¹⁾	—	CLCIN3⁽¹⁾	—	—	—	—	IOCA5	INT2⁽¹⁾	CLKIN SOSCI OSC1
RC0^{(7, 8)}	10	—	—	TUIN1⁽¹⁾	—	—	—	SCK1⁽¹⁾	SCL1^(3,4)	I3C1_SCL⁽⁵⁾	CTS2⁽¹⁾	IOCC0	—	—
RC1^{(7, 8)}	9	—	—	T4IN⁽¹⁾	PWM2ERS⁽¹⁾	—	CLCIN2⁽¹⁾	SDI1⁽¹⁾	SDA1^(3,4)	I3C1_SDA⁽⁵⁾	RX2⁽¹⁾	IOCC1	—	—
RC3	7	ANC3 ADACT⁽¹⁾	—	—	CCP2IN⁽¹⁾ PWMIN1⁽¹⁾	—	CLCIN0⁽¹⁾	SS1⁽¹⁾	—^(3,4)	—	—	IOCC3	—	—
RC4	6	ANC4	—	—	—	—	CLCIN1⁽¹⁾		—^(3,4)	—	CTS1⁽¹⁾	IOCC4	—	—
RC5	5	ANC5	—	—	CCP1IN⁽¹⁾ PWMIN0⁽¹⁾	—	—	—	—	—	RX1⁽¹⁾	IOCC5	—	—
V_DD^{(6 )}	1	—	—	—	—	—	—	—	—	—	—	—	—	V_DD
V_DDIO2^{(6 )}	8	—	—	—	—	—	—	—	—	—	—	—	—	V_DDIO2
V_SS	14	—	—	—	—	—	—	—	—	—	—	—	—	V_SS
OUT⁽²⁾	—	ADCGRDA ADCGRDB	—	TMR0 TU16A TU16B	PWM11 PWM12 PWM21 PWM22 CCP1 CCP2	CWG1A CWG1B CWG1C CWG1D	CLC1OUT CLC2OUT CLC3OUT CLC4OUT	SS1 SCK1 SDO1	SDA1 SCL1	—	DTR1 RTS1 TX1 DTR2 RTS2 TX2	—	—	—
Note: This is a PPS remappable input signal. The input function may be moved from the default location shown to one of several other PORTx pins. All digital output signals shown in these rows are PPS remappable. These signals may be mapped to output onto one of several PORTx pin options. This is a bidirectional signal. For normal module operation, the firmware will map this signal to the same pin in both the PPS input and PPS output registers. These pins are configured for I²C logic levels; the SCLx/SDAx signals may be assigned to any of these pins. PPS assignments to the other pins (e.g., RB1) will operate, but input logic levels will be standard LVBUF/ST as selected by the INLVL register, instead of the I²C specific or SMBus input buffer thresholds. These pins are configured for I3C® logic levels and are not PPS remappable. MVIO must be enabled on these pins to be compliant with the I3C bus standards. A 0.1 uF bypass capacitor to V_SS is required on the V_DD and V_DDIOx pins. MVIO pins, powered by V_DDIO2. High-voltage tolerant pins.

Table 3-2. 20-Pin Allocation Table
I/O	20-Pin PDIP/ SOIC/ SSOP	20-Pin VQFN	A/D	Reference	Timers	16-Bit PWM/CCP	CWG	CLC	SPI	I²C	I3C®	UART	IOC	Interrupts	Basic
RA0	19	16	ANA0	—	—	—	—	—	—	—	—	—	IOCA0	—	ICDDAT ICSPDAT
RA1	18	15	ANA1	VREF+ (ADC)	TUIN0⁽¹⁾	—	—	—	—	—	—	—	IOCA1	—	ICDCLK ICSPCLK
RA2	17	14	ANA2	VREF- (ADC)	T0CKI⁽¹⁾	—	CWG1IN⁽¹⁾	CLCIN0⁽¹⁾	—	—	—	—	IOCA2	INT0⁽¹⁾	—
RA3	4	1	—	—	—	—	—	—	—	—	—	—	IOCA3	—	MCLR V_PP
RA4	3	20	ANA4	—	T1G⁽¹⁾	—	—	—	—	—	—	—	IOCA4	INT1⁽¹⁾	CLKOUT SOSCO OSC2
RA5	2	19	ANA5	—	T2IN⁽¹⁾ T1CKI⁽¹⁾	PWM1ERS ⁽¹⁾	—	—	—	—	—	—	IOCA5	INT2⁽¹⁾	CLKIN SOSCI OSC1
RB5^{(8, 9)}	12	9	—	—	—	—	—	CLCIN3⁽¹⁾	SDI1⁽¹⁾	SDA1^(3,4)	I3C2_SDA⁽⁵⁾	RX1⁽¹⁾	IOCB5	—	—
RB6^{(8, 9)}	11	8	—	—	—	—	—	CLCIN2⁽¹⁾	SCK1⁽¹⁾	SCL1^(3,4)	I3C2_SCL⁽⁵⁾	—	IOCB6	—	—
RB7	10	7	ANB7	—	—	—	—	—	—	—	—	CTS1⁽¹⁾	IOCB7	—	—
RC0^{(7, 9)}	16	13	—	—	TUIN1⁽¹⁾	—	—	—	—	—^(3,4)	I3C1_SCL⁽⁵⁾	CTS2⁽¹⁾	IOCC0	—	—
RC1^{(7, 9)}	15	12	—	—	T4IN⁽¹⁾	PWM2ERS ⁽¹⁾	—	—	—	—^(3,4)	I3C1_SDA⁽⁵⁾	RX2⁽¹⁾	IOCC1	—	—
RC3	7	4	ANC3 ADACT⁽¹⁾	—	—	CCP2IN⁽¹⁾ PWMIN1⁽¹⁾	—	CLCIN1⁽¹⁾	—	—	—	—	IOCC3	—	—
RC4	6	3	ANC4	—	T3G⁽¹⁾	—	—	—	—	—^(3,4)	—	—	IOCC4	—	—
RC5	5	2	ANC5	—	T3CKI⁽¹⁾	CCP1IN⁽¹⁾ PWMIN0⁽¹⁾	—	—	—	—^(3,4)	—	—	IOCC5	—	—
RC6	8	5	ANC6	—	—	—	—	—	SS1⁽¹⁾	—	—	—	IOCC6	—	—
RC7	9	6	ANC7	—	—	—	—	—	—	—	—	—	IOCC7	—	—
V_DD⁽⁶⁾	1	18	—	—	—	—	—	—	—	—	—	—	—	—	V_DD
V_DDIO2⁽⁶⁾	14	11	—	—	—	—	—	—	—	—	—	—	—	—	V_DDIO2
V_DDIO3⁽⁶⁾	13	10	—	—	—	—	—	—	—	—	—	—	—	—	V_DDIO3
V_SS	20	17	—	—	—	—	—	—	—	—	—	—	—	—	V_SS
OUT⁽²⁾	—	—	ADCGRDA ADCGRDB	—	TMR0 TU16A TU16B	PWM11 PWM12 PWM21 PWM22 CCP1 CCP2	CWG1A CWG1B CWG1C CWG1D	CLC1OUT CLC2OUT CLC3OUT CLC4OUT	SS1 SCK1 SDO1	SDA1 SCL1	—	DTR1 RTS1 TX1 DTR2 RTS2 TX2	—	—	—
Note: This is a PPS remappable input signal. The input function may be moved from the default location shown to one of several other PORTx pins. All digital output signals shown in these rows are PPS remappable. These signals may be mapped to output onto one of several PORTx pin options. This is a bidirectional signal. For normal module operation, the firmware will map this signal to the same pin in both the PPS input and PPS output registers. These pins are configured for I²C logic levels; the SCLx/SDAx signals may be assigned to any of these pins. PPS assignments to the other pins (e.g., RB1) will operate, but input logic levels will be standard LVBUF/ST as selected by the INLVL register, instead of the I²C specific or SMBus input buffer thresholds. These pins are configured for I3C® logic levels and are not PPS remappable. MVIO must be enabled on these pins to be compliant with the I3C bus standards. A 0.1 uF bypass capacitor to V_SS is required on the V_DD and V_DDIOx pins. MVIO pins, powered by V_DDIO2. MVIO pins, powered by V_DDIO3. High-voltage tolerant pins.