24.8.4 CLCnSEL0

Generic CLCn Data 1 Select Register
Name: CLCnSEL0
Address: 0x1A7

Bit 76543210 
   D1S[5:0] 
Access R/WR/WR/WR/WR/WR/W 
Reset xxxxxx 

Bits 5:0 – D1S[5:0] CLCn Data1 Input Selection

Table 24-2. CLC Input Selection
DyS Input Source DyS (cont.) Input Source (cont.) DyS (cont.) Input Source (cont.)
[0] 0000 0000 CLCIN0PPS [16] 0001 0000 TMR0 [32] 0010 0000 CLC3
[1] 0000 0001 CLCIN1PPS [17] 0001 0001 TMR1 [33] 0010 0001 CLC4
[2] 0000 0010 CLCIN2PPS [18] 0001 0010 TMR2 [34] 0010 0010 U1TX
[3] 0000 0011 CLCIN3PPS [19] 0001 0011 TMR4 [35] 0010 0011 U2TX
[4] 0000 0100 FOSC [20] 0001 0100 TU16A [36] 0010 0100 SPI1_SDO
[5] 0000 0101 HFINTOSC(1) [21] 0001 0101 TU16B [37] 0010 0101 SPI1_SCK
[6] 0000 0110 LFINTOSC(1) [22] 0001 0110 CCP1 [38] 0010 0110 SPI1_SS
[7] 0000 0111 MFINTOSC(1) [23] 0001 0111 CCP2 [39] 0010 0111 I2C1_SCL
[8] 0000 1000 MFINTOSC (31.25 kHz)(1) [24] 0001 1000 PWM1S1P1_OUT [40] 0010 1000 I2C1_SDA
[9] 0000 1001 SFINTOSC (1 MHz)(1) [25] 0001 1001 PWM1S1P2_OUT [41] 0010 1001 I3C1_SCL
[10] 0000 1010 SOSC(1) [26] 0001 1010 PWM2S1P1_OUT [42] 0010 1010 I3C1_SDA
[11] 0000 1011 EXTOSC(1) [27] 0001 1011 PWM2S1P2_OUT [43] 0010 1011 I3C2_SCL
[12] 0000 1100 ADCRC(1) [28] 0001 1100 CWG1A [44] 0010 1100 I3C2_SDA
[13] 0000 1101 IOC [29] 0001 1101 CWG1B [45] 0010 1101 HLVD_OUT
[14] 0000 1110 IOCSR (Signal Routing Ports) [30] 0001 1110 CLC1 [46] 0010 1110 -
[15] 0000 1111 CLKR [31] 0001 1111 CLC2 [47] 0010 1111 -
Note:
  1. Requests clock.
Reset States: 
POR/BOR = xxxxxx
All Other Resets = uuuuuu