24.8.4 CLCnSEL0

Generic CLCn Data 1 Select Register
Name: CLCnSEL0
Address: 0x1A7

Bit 76543210 
   D1S[5:0] 
Access R/WR/WR/WR/WR/WR/W 
Reset xxxxxx 

Bits 5:0 – D1S[5:0] CLCn Data1 Input Selection

Table 24-2. CLC Input Selection
DyS Input SourceDyS (cont.)Input Source (cont.)DyS (cont.)Input Source (cont.)
[0] 0000 0000CLCIN0PPS[16] 0001 0000TMR0[32] 0010 0000CLC3
[1] 0000 0001CLCIN1PPS[17] 0001 0001TMR1[33] 0010 0001CLC4
[2] 0000 0010CLCIN2PPS[18] 0001 0010TMR2[34] 0010 0010U1TX
[3] 0000 0011CLCIN3PPS[19] 0001 0011TMR4[35] 0010 0011U2TX
[4] 0000 0100FOSC[20] 0001 0100TU16A[36] 0010 0100SPI1_SDO
[5] 0000 0101HFINTOSC(1)[21] 0001 0101TU16B[37] 0010 0101SPI1_SCK
[6] 0000 0110LFINTOSC(1)[22] 0001 0110CCP1[38] 0010 0110SPI1_SS
[7] 0000 0111MFINTOSC(1)[23] 0001 0111CCP2[39] 0010 0111I2C1_SCL
[8] 0000 1000MFINTOSC (31.25 kHz)(1)[24] 0001 1000PWM1S1P1_OUT[40] 0010 1000I2C1_SDA
[9] 0000 1001SFINTOSC (1 MHz)(1)[25] 0001 1001PWM1S1P2_OUT[41] 0010 1001I3C1_SCL
[10] 0000 1010SOSC(1)[26] 0001 1010PWM2S1P1_OUT[42] 0010 1010I3C1_SDA
[11] 0000 1011EXTOSC(1)[27] 0001 1011PWM2S1P2_OUT[43] 0010 1011I3C2_SCL
[12] 0000 1100ADCRC(1)[28] 0001 1100CWG1A[44] 0010 1100I3C2_SDA
[13] 0000 1101IOC[29] 0001 1101CWG1B[45] 0010 1101HLVD_OUT
[14] 0000 1110IOCSR (Signal Routing Ports)[30] 0001 1110CLC1[46] 0010 1110-
[15] 0000 1111CLKR[31] 0001 1111CLC2[47] 0010 1111-
Note:
  1. Requests clock.
Reset States: 
POR/BOR = xxxxxx
All Other Resets = uuuuuu