28.10.5 TxCLKCON

Timer Clock Source Selection Register

Name:	TxCLKCON
Address:	0x11D,0x123


Bit	7	6	5	4	3	2	1	0
					CS[3:0]
Access					R/W	R/W	R/W	R/W
Reset					0	0	0	0

Bits 3:0 – CS[3:0] Timer Clock Source Selection

Table 28-3. Clock Source Selection
CS	Clock Source
CS	Timer2	Timer4
`1111 - 1110`	Reserved
`1101`	CLC4_OUT
`1100`	CLC3_OUT
`1011`	CLC2_OUT
`1010`	CLC1_OUT
`1001`	CLKREF_OUT
`1000`	EXTOSC
`0111`	SOSC
`0110`	MFINTOSC (32 kHz)
`0101`	MFINTOSC (500 kHz)
`0100`	LFINTOSC
`0011`	HFINTOSC
`0010`	F_OSC
`0001`	F_OSC/4
`0000`	Pin selected by T2INPPS	Pin selected by T4INPPS