20.3.3 PORTWCLK

Signal Routing Port Clock Selection
Note: This register can only be written when the clock to the module is disabled. See Signal Routing Port Clock for details.
Name: PORTWCLK
Address: 0x04A3

Bit 76543210 
    CLK[4:0] 
Access R/WR/WR/WR/WR/W 
Reset 00000 

Bits 4:0 – CLK[4:0]  Signal Routing Port Clock Input Selection

Table 20-2. Signal Routing Port Clock Input Selections
CLKClock Input
11111 - 10110Reserved
10101CLC4_OUT
10100CLC3_OUT
10011CLC2_OUT
10010CLC1_OUT
10001PWM2S1P2_OUT
10000PWM2S1P1_OUT
01111PWM1S1P2_OUT
01110PWM1S1P1_OUT
01101CCP2_OUT
01100CCP1_OUT
01011TU16B_OUT
01010TU16A_OUT
01001TMR4_OUT
01000TMR2_OUT
00111CLKREF_OUT
00110EXTOSC
00101SOSC
00100MFINTOSC (32 kHz)
00011MFINTOSC (500 kHz)
00010LFINTOSC
00001HFINTOSC
00000FOSC
Reset States: 
POR/BOR = 00000
All Other Resets = 00000
This register can only be written when the clock to the module is disabled. See Signal Routing Port Clock for details.