11.4.2 Natural Order (Hardware) Priority

When vectored interrupts are enabled and more than one interrupt with the same user specified priority level is requested, the priority conflict is resolved by using a method called “Natural Order Priority”. Natural order priority is a fixed priority scheme that is based on the IVT.

Table 11-2. Interrupt Vector Priority Table
Vector

Number

Interrupt

source

Vector

Number

(cont.)

Interrupt

source

(cont.)

0x0Software Interrupt0x3EPWM3RINT
0x1HLVD (High/Low-Voltage Detect)0x3FPWM3GINT
0x2OSF (Oscillator Fail)0x40U2RX
0x3CSW (Clock Switching)0x41U2TX
0x4-0x42U2E
0x5CLC1 (Configurable Logic Cell)0x43U2
0x6-0x44TMR5
0x7IOC (Interrupt-On-Change)0x45TMR5G
0x8INT00x46CCP2
0x9ZCD (Zero-Cross Detection)0x47SCAN
0xAAD (ADC Conversion Complete)0x48U3RX
0xBACT (Active Clock Tuning)0x49U3TX
0xCCM1 (Comparator)0x4AU3E
0xDSMT1 (Signal Measurement Timer)0x4BU3
0xESMT1PRA0x4C-
0xFSMT1PWA0x4DCLC4
0x10ADT0x4E - 0x4F-
0x11 - 0x13-0x50INT2
0x14DMA1SCNT (Direct Memory Access)0x51CLC5
0x15DMA1DCNT0x52CWG2 (Complementary Waveform Generator)
0x16DMA1OR0x53NCO2
0x17DMA1A0x54DMA3SCNT
0x18SPI1RX (Serial Peripheral Interface)0x55DMA3DCNT
0x19SPI1TX0x56DMA3OR
0x1ASPI10x57DMA3A
0x1BTMR20x58CCP3
0x1CTMR10x59CLC6
0x1DTMR1G0x5ACWG3
0x1ECCP1 (Capture/Compare/PWM)0x5BTMR4
0x1FTMR00x5CDMA4SCNT
0x20U1RX0x5DDMA4DCNT
0x21U1TX0x5EDMA4OR
0x22U1E0x5FDMA4A
0x23U10x60U4RX
0x24 - 0x25-0x61U4TX
0x26PWM1RINT0x62U4E
0x27PWM1GINT0x63U4
0x28SPI2RX0x64DMA5SCNT
0x29SPI2TX0x65DMA5DCNT
0x2ASPI20x66DMA5OR
0x2B-0x67DMA5A
0x2CTMR30x68U5RX
0x2DTMR3G0x69U5TX
0x2EPWM2RINT0x6AU5E
0x2FPWM2GINT0x6BU5
0x30INT10x6CDMA6SCNT
0x31CLC20x6DDMA6DCNT
0x32CWG1 (Complementary Waveform Generator)0x6EDMA6OR
0x33NCO1 (Numerically Controlled Oscillator)0x6FDMA6A
0x34DMA2SCNT0x70-
0x35DMA2DCNT0x71CLC7
0x36DMA2OR0x72CM2
0x37DMA2A0x73NCO3
0x38I2C1RX0x74 - 0x77-
0x39I2C1TX0x78NVM
0x3AI2C10x79CLC8
0x3BI2C1E0x7ACRC (Cyclic Redundancy Check)
0x3C-0x7BTMR6
0x3DCLC30x7C - 0x8F-

The natural order priority scheme goes from high-to-low with increasing vector numbers, with 0 being the highest priority and decreasing from there.

For example, when two concurrently occurring interrupt sources that are both designated high priority, using the IPRx register will be resolved using the natural order priority (i.e., the interrupt with a lower corresponding vector number will preempt the interrupt with the higher vector number).

The ability for the user to assign every interrupt source to high- or low-priority levels means that the user program can give an interrupt with a low natural priority, a higher overall priority level.