40.1.4 Conversion Clock

The conversion clock source is selected with the CS bit. When CS = 1 the ADC clock source is an internal fixed-frequency clock referred to as ADCRC. When CS = 0 the ADC clock source is derived from F_OSC.

Important: When CS = 0, the clock can be divided using the ADCLK register to meet the ADC clock period requirements.

The time to complete one bit conversion is defined as the T_AD. Refer to Figure 40-2 for the complete timing details of the ADC conversion.

For correct conversion, the appropriate T_AD specification must be met. Refer to the ADC Timing Specifications table in the “Electrical Specifications” chapter for more details. The table below gives examples of appropriate ADC clock selections.

Table 40-1. ADC Clock Period (T_AD) Vs. Device Operating Frequencies^(1,3)
ADC Clock Source	ADCLK	ADC Clock Period (T_AD) for Different Device Frequency (F_OSC)
ADC Clock Source	ADCLK	64 MHz	32 MHz	20 MHz	16 MHz	8 MHz	4 MHz	1 MHz
F_OSC/2	`‘b000000`	31.25 ns⁽²⁾	62.5 ns⁽²⁾	100 ns⁽²⁾	125 ns⁽²⁾	250 ns⁽²⁾	500 ns	2.0 μs
F_OSC/4	`‘b000001`	62.5 ns⁽²⁾	125 ns⁽²⁾	200 ns⁽²⁾	250 ns⁽²⁾	500 ns	1.0 μs	4.0 μs
F_OSC/6	`‘b000010`	93.75 ns⁽²⁾	187.5 ns⁽²⁾	300 ns⁽²⁾	375 ns⁽²⁾	750 ns	1.5 μs	6.0 μs
F_OSC/8	`‘b000011`	125 ns⁽²⁾	250 ns⁽²⁾	400 ns⁽²⁾	500 ns	1.0 μs	2.0 μs	8.0 μs
...	...	...	...	...	...	...	...	...
F_OSC/16	`‘b000111`	250 ns⁽²⁾	500 ns	800 ns	1.0 μs	2.0 μs	4.0 μs	16.0 μs⁽²⁾
...	...	...	...	...	...	...	...	...
F_OSC/32	`‘b001111`	500 ns	1.0 μs	1.6 μs	2.0 μs	4.0 μs	8.0 μs	32.0 μs⁽²⁾
...	...	...	...	...	...	...	...	...
F_OSC/64	`‘b0111111`	1.0 μs	2.0 μs	3.2 μs	4.0 μs	8.0 μs	16.0 μs⁽³⁾	64.0 μs⁽²⁾
...	...	...	...	...	...	...	...	...
F_OSC/128	`‘b111111`	2.0 μs	4.0 μs	6.4 μs	8.0 μs	16.0 μs⁽²⁾	32.0 μs⁽²⁾	128.0 μs⁽²⁾
ADCRC	CS=`1`	1.0-6.0 μs	1.0-6.0 μs	1.0-6.0 μs	1.0-6.0 μs	1.0-6.0 μs	1.0-6.0 μs	1.0-6.0 μs
Note: Refer to the “Electrical Specifications” chapter to see the T_AD parameter for the ADCRC source typical T_AD value. These values violate the required T_AD time. The ADC clock period (T_AD) and total ADC conversion time can be minimized when the ADC clock is derived from the system clock F_OSC. However, the ADCRC oscillator source must be used when conversions are to be performed with the device in Sleep mode.

Important:

Except for the ADCRC clock source, any changes in the system clock frequency will change the ADC clock frequency, which may adversely affect the ADC result.
The internal control logic of the ADC runs off of the clock selected by the CS bit. When the CS bit is set to ‘1’ (ADC runs on ADCRC), there may be unexpected delays in operation when setting the ADC control bits.

Figure 40-2. Analog-to-Digital Conversion Cycles