12.5.8 OSCEN

Oscillator Enable Register
Note:
  1. This bit only controls external clock source supplied to the peripherals and has no effect on the system clock.
Name: OSCEN
Offset: 0x0B3

Bit 76543210 
 EXTOENHFOENMFOENLFOENSOSCENADOEN PLLEN 
Access R/WR/WR/WR/WR/WR/WR/W 
Reset 0000000 

Bit 7 – EXTOEN External Oscillator Enable

ValueDescription
1 EXTOSC is explicitly enabled, operating as specified by FEXTOSC
0 EXTOSC can be enabled by a peripheral request

Bit 6 – HFOEN HFINTOSC Enable

ValueDescription
1 HFINTOSC is explicitly enabled, operating as specified by OSCFRQ
0 HFINTOSC can be enabled by a peripheral request

Bit 5 – MFOEN MFINTOSC Enable

ValueDescription
1 MFINTOSC is explicitly enabled
0 MFINTOSC can be enabled by a peripheral request

Bit 4 – LFOEN LFINTOSC Enable

ValueDescription
1 LFINTOSC is explicitly enabled
0 LFINTOSC can be enabled by a peripheral request

Bit 3 – SOSCEN Secondary Oscillator Enable

ValueDescription
1 SOSC is explicitly enabled, operating as specified by SOSCPWR
0 SOSC can be enabled by a peripheral request

Bit 2 – ADOEN ADCRC Oscillator Enable

ValueDescription
1 ADCRC is explicitly enabled
0 ADCRC may be enabled by a peripheral request

Bit 0 – PLLEN  PLL Enable(1)

ValueDescription
1 EXTOSC multiplied by the 4x system PLL is used by a peripheral request
0 EXTOSC is used by a peripheral request
This bit only controls external clock source supplied to the peripherals and has no effect on the system clock.