36.2.5 Input and Output Polarity Control

SPIxCON1 has three bits that control the polarity of the SPI inputs and outputs:

• The SDIP bit controls the polarity of the SDI input
• The SDOP bit controls the polarity of the SDO output
• The SSP bit controls the polarity of both the client SS input and the host SS output

For all three bits, when the bit is clear, the input or output is active-high, and when the bit is set, the input or output is active-low. When the EN bit is cleared, SS_out and SCK_out both revert to the Inactive state dictated by their polarity bits. The SDO Output state, when the EN bit is cleared, is determined by several factors as follows:

• When the associated TRIS bit for the SDO pin is cleared and the SPI goes Idle after a transmission, the SDO output will remain at the last bit level.
• When the associated TRIS bit for the SDO pin is set, its behavior varies in Client and Host modes:
  • In Client mode, the SDO pin tri-states when any of the following is true:
    • Client Select is inactive
    • EN = 0
    • TXR = 0
  • In Host mode:
    • The SDO pin tri-states when TXR = 0
    • When TXR = 1 and the SPI goes Idle after a transmission, the SDO output will remain at the last bit level. The SDO pin will revert to the Idle state when EN is cleared.