38.11.2 FIFO Combined Interrupts

The following interrupts are individual FIFO interrupts:
  • FIFOs/TXQ: RFIFx, TFIFx, RFOVIFx and TFATIFx
They are combined into single Interrupt Status registers:
  • CxRXIF, CxTXIF, CxRXOVIF and CxTXATIF

The bits in the status registers are mapped to the FIFOs as follows: Bit 0 to TXQ, Bit 1 to FIFO 1, Bit 2 to FIFO 2, up to Bit 3 to FIFO 3. Since Bit 0 corresponds to the TXQ, Bit 0 of CxRXIF and CxRXOVIF is reserved. Hence, by reading one register, the application can check the status of all FIFOs for a particular interrupt (e.g., any RFIFx pending).

The FIFO interrupts are enabled in CxFIFOCONy.

TXQ interrupts are enabled in CxTXQCON.

Clearing of the FIFO interrupts is explained in FIFO Individual Interrupts.