39.1.1 TAP
The Test Access Port (TAP) on the PIC18-Q83 is a
general-purpose port that provides test access to many built-in support functions and
test logic defined in IEEE Standard 1149.1. The TAP is disabled by programming the
JTAGEN bit in CONFIG2 (the TAP, by default, is enabled in the
bit’s unprogrammed state). While enabled, the designated I/O pins become dedicated TAP
pins. The PIC implements a 4-pin JTAG interface with these pins:
- TCK (Test Clock): Provides the clock for test logic.
- TMS (Test Mode Select): Input used by the TAP to control test operations.
- TDI (Test Data Input): Serial input for test instructions and data.
- TDO (Test Data Output): Serial output for test instructions and data.
To minimize I/O loss due to JTAG, the optional TAP Reset (TRST) input pin, specified in the standard, is not implemented on PIC18-Q83 devices. For convenience, a “soft” TAP Reset has been included in the TAP controller, using the TMS and TCK pins. To force a port Reset, apply a logic high to the TMS pin for at least five rising edges of TCK. Note that device Resets (including POR) do not automatically result in a TAP Reset; this must be done by the external JTAG controller using the soft TAP Reset.