26.7 Operating Modes

The mode of the timer is controlled by the MODE bits. Edge Triggered modes require six Timer clock periods between external triggers. Level Triggered modes require the triggering level to be at least three Timer clock periods long. External triggers are ignored while in Debug mode.
Table 26-1. Operating Modes Table
Mode MODE Output

Operation

 Operation Timer Control
[4:3] [2:0] Start Reset Stop
Free-Running Period 00 000 Period Pulse Software gate (Figure 26-3) ON = 1 — ON = 0
001 Hardware gate, active-high

(Figure 26-4)

 ON = 1 and

TMRx_ers = 1

 — ON = 0 or

TMRx_ers = 0
010 Hardware gate, active-low ON = 1 and

TMRx_ers = 0

 — ON = 0 or

TMRx_ers = 1
011

Period Pulse

with

Hardware Reset

 Rising or falling edge Reset ON = 1 TMRx_ers ↕ ON = 0
100 Rising edge Reset (Figure 26-5) TMRx_ers ↑
101 Falling edge Reset TMRx_ers ↓
110 Low-level Reset TMRx_ers = 0 ON = 0 or

TMRx_ers = 0
111 High-level Reset (Figure 26-6) TMRx_ers = 1 ON = 0 or

TMRx_ers = 1
One Shot 01 000 One-shot Software start (Figure 26-7) ON = 1 — ON = 0

or

Next clock after

TxTMR = TxPR

(Note 2)
001

Edge-Triggered Start

(Note 1)

 Rising edge start (Figure 26-8) ON = 1 and

TMRx_ers ↑

 —
010 Falling edge start ON = 1 and

TMRx_ers ↓

 —
011 Any edge start ON = 1 and

TMRx_ers ↕

 —
100

Edge-Triggered Start

and

Hardware Reset

(Note 1)

 Rising edge start and

Rising edge Reset (Figure 26-9)

 ON = 1 and

TMRx_ers ↑

 TMRx_ers ↑
101 Falling edge start and

Falling edge Reset

 ON = 1 and

TMRx_ers ↓

 TMRx_ers ↓
110 Rising edge start and

Low-level Reset (Figure 26-10)

 ON = 1 and

TMRx_ers ↑

 TMRx_ers = 0
111 Falling edge start and

High-level Reset

 ON = 1 and

TMRx_ers ↓

 TMRx_ers = 1
Monostable 10 000 Reserved
001

Edge-Triggered Start

(Note 1)

 Rising edge start

(Figure 26-11)

 ON = 1 and

TMRx_ers ↑

 — ON = 0

or

Next clock after

TxTMR = TxPR

(Note 3)
010 Falling edge start ON = 1 and

TMRx_ers ↓

 —
011 Any edge start ON = 1 and

TMRx_ers ↕

 —
Reserved 100 Reserved
Reserved 101 Reserved
One Shot 110

Level-Triggered Start

and

Hardware Reset

 High-level start and

Low-level Reset (Figure 26-12)

 ON = 1 and

TMRx_ers = 1

 TMRx_ers = 0 ON = 0 or

Held in Reset

(Note 2)
111 Low-level start and

High-level Reset

 ON = 1 and

TMRx_ers = 0

 TMRx_ers = 1
Reserved 11 xxx Reserved
Note:
  1. If ON = 0, then an edge is required to restart the timer after ON = 1.
  2. When T2TMR = T2PR, the next clock clears ON and stops T2TMR at 00h.
  3. When T2TMR = T2PR, the next clock stops T2TMR at 00h but does not clear ON.