25.13.4 TxGATE

Timer Gate Source Selection Register

Name:	TxGATE
Offset:	0x320,0x32C,0x338


Bit	7	6	5	4	3	2	1	0
			GSS[5:0]
Access			R/W	R/W	R/W	R/W	R/W	R/W
Reset			0	0	0	0	0	0

Bits 5:0 – GSS[5:0] Timer Gate Source Selection

Table 25-5. Timer Gate Sources
GSS	Gate Source
GSS	Timer1	Timer3	Timer5
`111111-100010`	Reserved
`100001`	CLC8_OUT
`100000`	CLC7_OUT
`011111`	CLC6_OUT
`011110`	CLC5_OUT
`011101`	CLC4_OUT
`011100`	CLC3_OUT
`011011`	CLC2_OUT
`011010`	CLC1_OUT
`011001`	ZCD_OUT
`011000`	CMP2_OUT
`010111`	CMP1_OUT
`010110`	NCO3_OUT
`010101`	NCO2_OUT
`010100`	NCO1_OUT
`010011`	PWM4S1P2_OUT
`010010`	PWM4S1P1_OUT
`010001`	PWM3S1P2_OUT
`010000`	PWM3S1P1_OUT
`001111`	PWM2S1P2_OUT
`001110`	PWM2S1P1_OUT
`001101`	PWM1S1P2_OUT
`001100`	PWM1S1P1_OUT
`001011`	CCP3_OUT
`001010`	CCP2_OUT
`001001`	CCP1_OUT
`001000`	SMT1_OUT
`000111`	TMR6_Postscaler_OUT
`000110`	TMR5_OUT	TMR5_OUT	Reserved
`000101`	TMR4_Postscaler_OUT
`000100`	TMR3_OUT	Reserved	TMR3_OUT
`000011`	TMR2_Postscaler_OUT
`000010`	Reserved	TMR1_OUT	TMR1_OUT
`000001`	TMR0_OUT
`000000`	Pin selected by T1GPPS	Pin selected by T3GPPS	Pin selected by T5GPPS

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