38.3.4.4 Receive FIFO Configuration

FIFO 1 through FIFO 3 can be configured as receive FIFOs by clearing TXEN in the CxFIFOCONy register. The number of message objects in each receive FIFO is configured using the FSIZE[4:0] bits (CxFIFOCONy[27:23]). All objects in one receive FIFO use the same payload size (number of data bytes), which is determined by the PLSIZE[2:0] bits (CxFIFOCONy[30:28]). Received messages can be timestamped by setting the RXTSEN bit (CxFIFOCONy[5]).