1 Silicon Errata Summary
| Module | Feature | Issue Summary | Affected Revisions | |
|---|---|---|---|---|
| PIC32CX5109BZ31048, WBZ351 | PIC32CX5109BZ31032, WBZ350 | |||
| A0 | ||||
| Supply Voltage and Power Mode | Device parts are not powering at 1.9V | Device parts are not powering at 1.9V | X | |
| Supply Voltage and Power Mode | Power Management Support | The PIC32CX-BZ3 Power Management Unit (PMU) supports only the MLDO mode in the revision “A0” of silicon and supports the Buck mode in the revision “B0” of silicon. | X | |
| Supply Voltage and Power Mode | System Does Not Enter Sleep Mode
with Flash Power Down (NVMCON2.SLEEP = 0) Bit Disabled and System
Clock Equal to or Less than the FRC Frequency |
The system is not entering the Sleep
mode when the Flash power down (NVMCON2.SLEEP = 0) bit
is disabled and the system is working at FRC frequency. |
X | |
| Supply Voltage and Power Mode | GPIO Output Configuration in Deep Sleep and Extreme Deep Sleep |
In the Deep Sleep and Extreme Deep Sleep mode, GPIO must not be set to the output state of pin HIGH. Configuring the GPIO state to pin High during the Deep Sleep mode or Extreme Deep Sleep mode will causes leakage current and potential reliability issues on the silicon. This issue is only applicable when the CPU is in the Deep Sleep mode or Extreme Deep Sleep mode and when GPIO is configured as the output state pin HIGH. |
X | |
| Supply Voltage and Power Mode | POR Rearm Event | The POR event is not getting triggered even when the voltage is going below 1.45V. | X | |
| Analog Comparator (AC) | AC_CMPx Output is Not Gated Either by COMPCTRLx.ENABLE or PMD1.ACMD | The Analog Comparator output (AC_CMPx)
will not be disabled by setting either COMPCTRLx.ENABLE =
0 or PMD1.ACMD = 1. |
X | |
| Analog Comparator (AC) | Wrong VDD Scaler Reference for AC_CMP0 | AC_CMP0 uses a fixed VDD/2 reference, but the observed reference voltage is not equal to VDD/2. | X | |
| Analog Comparator (AC) | Wrong VDD Scaler Reference with CMP0 and CMP1 Enabled Concurrently | An incorrect VDD scaler reference voltage is observed when AC_CMP0 and AC_CMP1 are enabled concurrently with VDD scaler as reference for both the comparators. Both comparators will see the same VDD scaler reference. | X | |
| Analog-to-Digital Converter (ADC) | Scan | The scan list conversions defined in the ADCCSS1 register will restart without finishing the current scan list and does not generate an EOSRDY bit (ADCCON2[29]) end of scan interrupt status if a new trigger event from the STRGSRC[4:0] bits (ADCCON1[20:16]) trigger source occurs before the scan list completion on the shared ADC core. | X | |
| Analog-to-Digital Converter (ADC) | Glitches in ADC Conversion Result | When the ADC Control clock is asynchronous with the System clock, the conversion result may have glitches if the CPU reads ADCBUFx while the new conversion result is being updated. | X | |
| Analog-to-Digital Converter (ADC) | Wrong VDD33/2 for ADC Internal Input Channel AN11 | The ADC internal input channel, AN11, is connected with VDD33/2, but the observed input voltage is not equal to VDD/2. | X | |
| Capacitive Voltage Divider (CVD) Controller | False CVD event | An invalid CVD event can be created while the FIFO counter is incrementing. | X | |
| Direct Memory Access Controller (DMAC) | Linked Descriptors | When at least one channel using linked descriptors is already active, a channel Fetch Error (FERR) may occur, enabling a channel with no linked descriptor. Or when one of the already active channels using linked descriptors fetches the enabled second descriptor (index 1) of the channel. These errors can occur when a channel is enabled during the link request of another channel, and if the channel number of the enabled channel is lower than the already active channel. | X | |
| External Interrupt Controller (EIC) | Edge Detection | When enabling EIC, the SYNCBUSY.ENABLE bit resets before EIC is fully enabled. Edge detection can be done only after three cycles of the selected GCLK (GCLK_EIC or 32KHz_LPCLK). | X | |
| External Interrupt Controller (EIC) | Asynchronous Edge detection | When the asynchronous edge detection is enabled and the system is in the Standby Sleep mode, only the first edge will be detected. The edges following the first edge of the waveform are ignored until the system wakes up. | X | |
| External Interrupt Controller (EIC) | Asynchronous Edge Detection | When the asynchronous edge detection is enabled (without debouncer) and the system is in the Standby Sleep mode, only the first edge will generate an event. The edges following the first edge of the waveform do not generate events until the system wakes up. | X | |
| Event System (EVSYS) | Software Event | The BUSYCH flag never resets upon software events in synchronous/resynchronized path modes with event detection on falling edges. | X | |
| Event System (EVSYS) | Spurious Overrun | The overrun interrupt flag may be incorrectly set upon software events in synchronous/resynchronized path modes with event detection on both rising and falling edges. | X | |
| Event System (EVSYS) | Spurious Overrun | In the Synchronous mode, spurious
overrun interrupts can happen when the generic clock for a channel is
always CHANNEL.ONDEMAND = 0. |
X | |
| Flash Controller Module | SYS Reset Not Getting Released when Asserted Post-Erase Retry | After the Erase Retry operation (using
NVMCON2.VREAD1 = 1), all the operations work as
expected until a SYS reset is asserted. After the SYS reset is asserted
post-Erase Retry, the reset is stuck and is not being released. |
X | |
| Flash Controller Module | DMA in Sleep Mode | The Flash read/write by DMA is not working in Standby Sleep mode if the Flash power down is enabled. | X | |
| Peripheral Access Controller (PAC) | PAC Protection Error in FREQM | FREQM reads on the Control B register (FREQM.CTRLB) generate a PAC protection error. | X | |
| Quad I/O Serial Peripheral Interface (QSPI) | QSPI Status Register Bits Not Updated when PB-Bridge-B (PB2_CLK) is Not Equal to System Clock (SYS_CLK) | QSPI Status register bits not updated when PB-Bridge-B (PB2_CLK) are not equal to System Clock (SYS_CLK). | X | |
| RAM Error Correction Code (RAMECC) | ERRADDR Register May Read as
‘0’ When PB-Bridge-B (PB2_CLK) is Not Equal to System Clock
(SYS_CLK) |
If PB2_CLK is not equal to the System
clock (sys_clk), the ERRADDR register read will not return the failing
address (caused by Single Bit Error/Dual Bit Error); instead, it may
return ‘0’. |
X | |
| Real-Time Counter (RTC) | Write Corruption | An 8-bit or 16-bit write access for a
32-bit register or an 8-bit write access for a 16-bit register can fail
for the following registers:
|
X | |
| Real-Time Counter (RTC) | COUNTSYNC | When COUNTSYNC is enabled, the first COUNT value is not correctly synchronized and, thus, the value is incorrect. | X | |
| Real-Time Counter (RTC) | Tamper Input Filter | Majority debouncing, as part of RTC tamper detection, does not work when enabled by setting the Debouncer Majority Enable bit, CTRLB.DEBMAJ. | X | |
| Real-Time Counter (RTC) | Tamper Detection | Upon enabling the RTC tamper detection feature, a false tamper detection can be reported by the RTC. | X | |
| Real-Time Counter (RTC) | Tamper Detection Timestamp |
If an external Reset occurs during a tamper detection, the TIMESTAMP register will not be updated when the next tamper detection is triggered. |
X | |
| Real-Time Counter (RTC) | Periodic Event Generation | When CTRLA.PRESCALER is set to OFF and either CTRLB.RTCOUT is set or one of the TAMCTRL.DEBNCn bits is set, the RTC prescaler behaves like CTRLA.PRESCALER = DIV1. The Periodic events and Periodic interrupts will be generated. | X | |
| Real-Time Counter (RTC) | General Purpose Register |
General Purpose Registers n (GPn) are Reset on tamper detection even
if GPTRST = |
X | |
| Real-Time Counter (RTC) | Tamper Detection | False tamper detections may occur when configuring the RTC INn and OUTn pins. | X | |
| Real-Time Counter (RTC) | SYNCBUSY Register | Entering the Deep Sleep mode without waiting for SYNCBUSY.ENABLE and SYNCBUSY.COUNTSYNC synchronization completion may freeze these bits statuses. | X | |
| Real-Time Counter (RTC) | TIMESTAMP Lock by INFLAG.TAMPER | Clear the INTFLAG.TAMPER bit by writing
a ‘1’ to this bit when the Timestamp value was read
from the TIMESTAMP register. |
X | |
| Serial Communication Interface (SERCOM) | SERCOM-USART: Collision Detection | In the USART operating mode, if
DBGCTRL.DBGSTOP = 1, data transmission is not halted
after entering the Debug mode. |
X | |
| Serial Communication Interface (SERCOM) | SERCOM-USART: Debug Mode | The 32-bit Extension mode is enabled and data to be sent is not in multiples of 4 bytes, which means the length counter must be enabled, and additional bytes will be sent over the line. | X | |
| Serial Communication Interface (SERCOM) | SERCOM-USART: 32-Bit Extension Mode | The TXINV and RXINV bits in CTRLA are interchanged. TXINV controls the RX signal inversion and RXINV controls the TX signal inversion. | X | |
| Serial Communication Interface (SERCOM) | SERCOM-USART: TXINV and RXINV Bits | When the USART is used in the 32-bit
mode with hardware handshaking (CTS/RTS), the TXC flag may be set before
the transmission is complete. TXC may incorrectly be set regardless of
whether Data Length Enable (LENGTH.LENEN) is set to ‘0’
or ‘1’. |
X | |
| Serial Communication Interface (SERCOM) | SERCOM-USART: Flow Control in 32-Bit Extension Mode | The SERCOM USART does not wake from the Standby Sleep mode for ERROR interrupts FERR and PERR. | X | |
| Serial Communication Interface (SERCOM) | SERCOM-USART: Error Interrupts | When the SERCOM USART is configured as
CTRLA.RUNSTDBY = 0 and the Receiver is disabled
(CTRLB.RXEN = 0), the clock request to the SERCOM
generic clock generator feeding the SERCOM will stay asserted during the
Standby Sleep mode, leading to unexpected overconsumption. |
X | |
| Serial Communication Interface (SERCOM) | SERCOM-USART: SERCOM USART in TX Mode Only | The STATUS.CLKHOLD bit in the Host and Client modes can be written even though it is specified as a read-only status bit. | X | |
| Serial Communication Interface (SERCOM) | SERCOM-I2C: STATUS.CLKHOLD Bit in the Host and Client Modes | In the I2C mode, LENERR, SEXTOUT, LOWTOUT, COLL and BUSERR bits are not cleared when INTFLAG.AMATCH is cleared. | X | |
| Serial Communication Interface (SERCOM) | SERCOM-I2C: I2C in Client Mode | In the I2C Client Transmitter mode, at the reception of a NACK, if there are still data to be sent in the DMA buffer, the DMA will push data to the DATA register. Because a NACK was received, the transfer on the I2C bus will not occur, causing the loss of this data. | X | |
| Serial Communication Interface (SERCOM) | SERCOM-I2C: Client Mode with DMA | When SERCOM is configured as an
I2C client in the 32-bit Data mode (DATA32B =
1) and the I2C host reads from the
I2C client (client transmitter) and outputs its NACK
(indicating no more data is needed), the I2C client still
receives a DRDY interrupt. If the CPU does not write a new data to the
I2C client DATA register, the I2C client will
pull the SDA line, which will result in stalling the bus
permanently. |
X | |
| Serial Communication Interface (SERCOM) | SERCOM-I2C: I2C Client in DATA32B Mode |
When SERCOM is configured as an I2C client in the 32-bit
Data mode (DATA32B = If the CPU does not write a new data to the I2C client DATA register, the I2C client will pull the SDA line, which will result in stalling the bus permanently. |
X | |
| Serial Communication Interface (SERCOM) | SERCOM-I2C: Repeated Start | When the Quick command is enabled
(CTRLB.QCEN = 1), software can issue a repeated Start
by writing either CTRLB.CMD or ADDR.ADDR bit fields. If in these
conditions the SCL Stretch mode is CTRLA.SCLSM = 1, a
bus error will be generated. |
||
| Serial Communication Interface (SERCOM) | SERCOM-I2C: 10-Bit Addressing Mode | The 10-bit addressing in the I2C Client mode is not functional. | X | |
| Serial Communication Interface (SERCOM) | SERCOM-I2C: Repeated Start | For the Host Write operations (excluding the High-Speed mode), in 10-bit addressing mode, writing CTRLB.CMD = 0x1 does not issue a Repeated Start command correctly. | X | |
| Serial Communication Interface (SERCOM) | SERCOM-I2C Client: Error Interrupt INTFLAG.ERROR Repeated Start | When an unexpected STOP occurs on the I2C bus, the STATUS.BUSERR and INTFLAG.ERROR bits are set but may not wake the system from the Standby Sleep mode. An unexpected START will not produce this issue. | X | |
| Serial Communication Interface (SERCOM) | SERCOM-SPI: Data Preload | In the SPI Client mode with Client Data
Preload Enabled (CTRLB.PLOADEN = 1), the client
transmitter may discard some data if the host cannot keep the Client
Select pin low until the end of transmission. |
X | |
| Serial Communication Interface (SERCOM) | SERCOM-SPI: Client Data Preload | Preloading a new SPI data (CTRLB.PLOADEN
= 1) before going into the Standby Sleep mode may lead
to extra power consumption. |
X | |
| Serial Communication Interface (SERCOM) | SERCOM-SPI: Hardware Client Select Control | When Hardware Client Select Control is
enabled (CTRLB.MSSEN = 1), the Client Select (SS) pin
goes high after each byte transfer even if new data is ready to be
sent. |
X | |
| Serial Communication Interface (SERCOM) | I2C Client Auto Ack is Not Usable | The I2C client AACKEN feature is not usable when doing a repeated start. | X | |
| Timer/Counter for Control Applications (TCC) | Re-trigger in RAMP2 Operations | A re-trigger in RAMP2 operations (RAMP2,
RAMP2A, RAMP2C) is not supported if a prescaler is used (CTRLA.PRESCALER
! = 0), and the re-trigger of the counter is done on
the next GCLK (CTRLA.PRESCSYNC = GCLK or CTRLA.PRESCSYNC =
RESYNC). |
X | |
| Timer/Counter for Control Applications (TCC) | Re-trigger | If a Re-trigger event (EVCTRL.EVACTn = 0x1, RETRIGGER) occurs at the Channel Compare Match [n] time, the next Waveform Output [n] is corrupted. | X | |
| Timer/Counter for Control Applications (TCC) | TCC with EVSYS in SYNC/RESYNC Mode | The TCC peripheral is not compatible with an EVSYS channel in the SYNC or RESYNC mode. | X | |
| Timer/Counter for Control Applications (TCC) | Dithering Mode with External Re-trigger Events | Using the TCC in the Dithering mode with external retrigger events can lead to an unexpected stretch of right-aligned pulses or shrink of left-aligned pulses. | X | |
| Timer/Counter for Control Applications (TCC) | LUPD Feature in Down-Counting Mode | When the TCC is used in the Down-counting mode, transfer of PERBUF register value to PER register is delayed by one counter cycle and, therefore, the LUPD feature must not be used with the PER register. | X | |
| Timer/Counter for Control Applications (TCC) | RAMP2 Feature in Down-Counting Mode | The Timer/Counter counting-down mode
(CTRLBCLR.DIR = CTRLBSET.DIR = 1) is not supported in
RAMP2 operations (RAMP2, RAMP2A, RAMP2C, RAMP2CS). |
X | |
| Timer/Counter for Control Applications (TCC) | ALOCK Feature | The ALOCK feature is not functional. | X | |
| Timer/Counter for Control Applications (TCC) | In 2RAMP Mode with Hi-resolution Reference | In 2RAMP mode with Hi-resolution, multiple restarts can be observed when a fault occurred. | X | |
| Timer/Counter for Control Applications (TCC) | MCx Interrupt Status Flag is Not Cleared Automatically | In a capture operation, MC0/MC1 interrupt status flags (INTFLAG.MC0/INTFLAG.MC1) are not automatically cleared when the CC0/CC1 registers are read. | X | |
| Timer/Counter (TC) | PERBUF/CCBUFx Register | When clearing the STATUS.PERBUFV/STATUS.CCBUFx flag, the SYNCBUSY flag is released before the PERBUF/CCBUFx register is restored to its appropriate value. | X | |
| Timer/Counter (TC) | Re-trigger | If a Re-trigger event (EVCTRL.EVACTn = 0x1, RETRIGGER) occurs at the Channel Compare Match [n] time, the next Waveform Output [n] is corrupted. | X | |
| Timer/Counter (TC) | PER Register Reference | In the 8-bit mode, the PER register updates using the DMA are not possible in the Standby mode. | X | |
| Timer/Counter (TC) | MCx Interrupt Status Flag is Not Cleared Automatically | In capture operation, MC0/MC1 interrupt status flags (INTFLAG.MC0/INTFLAG.MC1) are not automatically cleared when the CC0/CC1 registers are read. | X | |
| Watchdog Timer (WDT) | RUN Mode WDT Counter is Not Cleared Before Standby Sleep Instruction |
When the interval between clearing the watch dog timer and the sleep instruction is less than 1 WDT clock cycle, the Run mode watchdog counter is not cleared. While in the Standby Sleep mode, the Sleep mode watchdog counter is incrementing, and, at the end of the WDTPS, it generates an NMI which causes the CPU to wake up. After wake-up, the user will expect that because WDT is cleared just before going to sleep, they have an entire WDT period available to them before they have to clear WDT again. But because the Run mode counter was not cleared before going into sleep, the WDT Reset will occur earlier than expected. |
X | |
Note:
- Cells with ‘X’ indicate the issue is present in this revision of the silicon.
- Cells with ‘—’ indicate the issue does not exist in this revision of the silicon.
- The blank cell indicates the issue is corrected or does not exist in this revision of the silicon.