3.4.6 Gigabit Ethernet Interface

The SAM9X75-Curiosity board embeds a modular Ethernet PHY system (Gigabit Ethernet Interface through SODIMM connector) that enables different PHYs and switches to be plugged into the board. This interface is set up to use one Reduced Gigabit Media-Independent Interface (RGMII), a PTP interface, SERDES interfaces and an I²C bus interface with GPIO.

The same connector also provides an SPI communication bus for compatible daughter boards. In order to enable the SPI communication, jumper JP5 needs to be connected between positions two and three of the J11 header.

The following figure shows the Gigabit Ethernet interface.

Figure 3-27. Gigabit Ethernet Interface

The following table shows the Gigabit Ethernet interface signal description.

Table 3-15. Gigabit Ethernet Interface Signal Description
Pin No.	PIO	Signal Name	Signal Description
1, 3, 5	–	5V_MAIN	5V
2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30, 37, 43, 51, 52, 55, 56, 60, 61, 67, 68, 72, 73, 76, 79, 80, 84, 85, 91, 92, 95, 96, 99, 100, 103, 104, 106, 107, 108, 110, 111, 112, 114, 115, 116, 118, 119, 120, 122, 123, 124, 126, 127, 128, 130, 131, 132, 134, 135, 136, 138, 139, 140, 142, 143, 144, 145, 146, 149, 151, 155, 159, 163, 167, 171, 175, 179, 183, 187, 191, 195, 199, 203	–	GND	Ground
9, 11, 13	–	VDD_3V3_B	3.3V
17, 19, 21	–	VDD_2V5_B	2.5V
25, 27, 29	–	VARIO_ETH	3.3V
31	PC23	GIGABIT_SPI_MISO	SPI Host Input Signal
32	–	GIGABIT_ETH_ PHYID	Pull-Down
33	PC22	GIGABIT_SPI_MOSI	SPI Host Output Signal
34	–	GIGABIT_ETH_MDETECT	Pull-Up
35	PC26	GIGABIT_SPI_SCK	SPI Clock Signal
38	PC25	GIGABIT_SPI_NPCS0	SPI Chip Select signal
39	PC1	GIGABIT_ETH_I²C_CLK_PC1	TWI Clock
41	PC0	GIGABIT_ETH _I²C_DATA_PC0	TWI Data
42	NRST or PC25	NRST or NRST_OUT	Reset
45	PB10	GIGABIT_ETH_MDC	Management Data Clock
47	PB9	GIGABIT_ETH_MDIO	Management Data Input/Output
49	PD5	GIGABIT_ETH_IRQ_N	Interrupt
53	–	RGMII_25MHZ	Clock 25 MHz
62	PB2	GIGABIT_ETH_125CK	125 MHz Clock
93	PB7	RGMII_TXCTL/GMII_TXEN	Transmit Enable or Transmit Control
97	PB6	RGMII_TXC-TXCK/GMII_TXCLK	Transmit Clock
101	PB13	RGMII_TXD0/GMII_TXD0	Transmit Data 0
105	PB14	RGMII_TXD1/GMII_TXD1	Transmit Data 1
109	PB4	RGMII_TXD2/GMII_TXD2	Transmit Data 2
113	PB5	RGMII_TXD3/GMII_TXD3	Transmit Data 3
117	PB3	RGMII_RXCTL/GMII_RXDV	Receive Control or Receive Data Valid
121	PB8	RGMII_RXC-RXCK/GMII_RXCLK	Receive Clock
125	PB11	RGMII_RXD0/GMII_RXD0	Receive Data 0
129	PB12	RGMII_RXD1/GMII_RXD1	Receive Data 1
133	PB0	RGMII_RXD2/GMII_RXD2	Receive Data 2
137	PB1	RGMII_RXD3/GMII_RXD3	Receive Data 3