1 DDR3L SDRAM Features

The SAM9X75 SiP is available with 1-Gbit and 2-Gbit DDR3L SDRAM memory options.

For power consumption, electrical characteristics and timings of these memories, refer to the manufacturer’s documentation listed in Reference Documents.

  • Power supply: DDRM_VDD = 1.283V to 1.45V
  • 2-Kbyte page size (x16)
  • 8-bank operation controlled by BA0, BA1 and BA2
  • Burst lengths (BL): 8 and 4 with Burst Chop (BC)
  • Precharge: auto-precharge option for each burst access
  • Auto-Refresh and Self-Refresh modes
  • Average refresh period:
    • 7.8 µs at tJ ≤ +85°C
    • 3.9 µs at tJ ≤ +105°C
    • 1.95 µs at tJ ≤ +125°C
  • High-speed data transfer realized by the 8-bit prefetch pipelined architecture
  • Double Data Rate architecture: two data transfers per clock cycle
  • Bidirectional differential data strobe (DQS and /DQS) transmitted/received with data for capturing data at the receiver
  • DQS edge-aligned with data for reads and center-aligned with data for writes
  • Differential clock inputs (CK and /CK)
  • DLL aligns DQ and DQS transitions with CK transitions
  • Commands entered on each positive CK edge; data and data mask referenced to both edges of DQS
  • Data mask (DM) for write data
  • Posted CAS by programmable additive latency for better command and data bus efficiency
  • MultiPurpose Register (MPR) for predefined pattern read out
  • ZQ calibration for DQ drive and ODT
  • Programmable Partial Array Self-Refresh (PASR)
  • Reset pin for power-up sequence and reset function
  • Self-Refresh Temperature (SRT) range: normal/extended
  • Automatic Self-Refresh (ASR)
  • Programmable output driver impedance control