6 Appendix B

This section provides information about the device IDs, checksums and pinout descriptions.

Table 6-1. Programming Pin Locations by Package Type
DevicePackagePackage CodeVDDVSSMCLRICSPCLKICSPDAT
PINPINPINPORTPINPORTPINPORT

PIC18F25Q43

PIC18F26Q43

PIC18F27Q43

28-Pin SPDIP(SP)2019, 81RE327RB628RB7
28-Pin SOIC(SO)2019, 81RE327RB628RB7
28-Pin SSOP(SS)2019, 81RE327RB628RB7
28-Pin VQFN(STX)1716, 526RE324RB625RB7

PIC18F45Q43

PIC18F46Q43

PIC18F47Q43

40-Pin PDIP(P)32, 1131, 121RE339RB640RB7
40-Pin QFN(MP)26, 727, 616RE314RB615RB7
44-Pin TQFP(PT)28, 729, 618RE316RB617RB7

PIC18F55Q43

PIC18F56Q43

PIC18F57Q43

48-Pin TQFP(Y8X)30, 731 , 620RE318RB619RB7
48-Pin VQFN(6LX)30, 731, 620RE318RB619RB7
Note:

The most current package drawings are located in the Microchip Packaging Specification, DS00000049 (http://www.microchip.com/packaging). The drawing numbers listed above do not include the current revision designator, which is added at the end of the number.