25 TMR1 - Timer1 Module with Gate Control

The Timer1 module is a 16-bit timer/counter with the following features:

  • 16-bit timer/counter register pair (TMRxH:TMRxL)
  • Programmable internal or external clock source
  • 2-bit prescaler
  • Clock source for optional comparator synchronization
  • Multiple Timer1 gate (count enable) sources
  • Interrupt-on-overflow
  • Wake-up on overflow (external clock, Asynchronous mode only)
  • 16-bit read/write operation
  • Time base for the capture/compare function with the CCP modules
  • Special event trigger (with CCP)
  • Selectable gate source polarity
  • Gate Toggle mode
  • Gate Single Pulse mode
  • Gate value status
  • Gate event interrupt
Important: References to the module Timer1 apply to all the odd numbered timers on this device.
Figure 25-1. Timer1 Block Diagram
Note:
  1. This signal comes from the pin selected by Timer1 PPS register.
  2. TMRx register increments on rising edge.
  3. Synchronize does not operate while in Sleep.
  4. See TxCLK for clock source selections.
  5. See TxGATE for gate source selections.
  6. Synchronized comparator output must not be used in conjunction with synchronized input clock.