33.3.8 Sleep Mode Operation

By default, the ADC is disabled in Standby sleep mode.

The ADC can stay fully operational in Standby sleep mode if the Run in Standby (RUNSTDBY) bit in the Control A (ADCn.CTRLA) register is written to ‘1’.

In this case, the ADC will stay active, any ongoing conversions will be completed, and interrupts will be executed as configured.

In Standby sleep mode, an ADC conversion can be triggered only via the Event System (EVSYS), or the ADC must be in Free-Running mode with the first conversion triggered by software before entering sleep. The peripheral clock is requested if needed and is turned off after the conversion is completed.

The reference source and supply infrastructure need time to stabilize when activated in Standby sleep mode. Configure a delay for the start of the first conversion by writing a non-zero value to the Initialization Delay (INITDLY) bit field in the Control D (ADCn.CTRLD) register.

In Power-Down sleep mode, no conversions are possible. Any ongoing conversions are halted and will be resumed when going out of sleep. At the end of the conversion, the Result Ready (RESRDY) flag will be set, but the content of the Result (ADCn.RES) registers will be invalid since the ADC was halted during a conversion. It is recommended to make sure conversions have completed before entering Power-Down sleep mode.

When going out of the Power-Down sleep mode or Standby sleep mode (when RUNSTDBY bit is cleared), the warm up time t_{warm_up} is needed. This delay can be implemented manually in code or by configuring the Initialization Delay (INITDLY) bit field in the Control D (ADCn.CTRLD) register to a value ≥ t_{warm_up} x f_{CLK_ADC}. Refer to the Electrical Characteristics section for further information.