In One Ramp mode, the TCD counter counts up until it reaches the CMPBCLR value. Then, the
TCD cycle is completed, and the counter restarts from 0x000, beginning
a new TCD cycle. The TCD cycle period is:
Figure 25-3. One Ramp Mode
In the figure above, CMPASET < CMPACLR < CMPBSET < CMPBCLR. In One Ramp
mode, this is required to avoid overlapping outputs during the on-time. The figure below
is an example where CMPBSET < CMPASET < CMPACLR < CMPBCLR, which has
overlapping outputs during the on-time. Figure 25-4. One Ramp Mode with CMPBSET
< CMPASETA match with CMPBCLR will always result in all outputs being cleared. If any of
the other compare values are bigger than CMPBCLR, their associated effect will never
occur. If the CMPACLR is smaller than the CMPASET value, the clear value will not have
any effect.
The online versions of the documents are provided as a courtesy. Verify all content and data in the device’s PDF documentation found on the device product page.
