7.1 Interrupt Management

The LAN8650/1 integrated PHY supports multiple interrupt capabilities which are not part of the IEEE 802.3 specification. When selected PHY status events are detected as configured by the PHY Interrupt Mask Registers, the PHY Interrupt (PHYINT) status bit in the OPEN Alliance Status 0 (OA_STATUS0) register is set. If further enabled by PHY Interrupt Mask (PHYINTM) bit in the OPEN Alliance Interrupt Mask 0 (OA_IMASK0) register, the IRQ_N pin will be asserted low.

To assert the PHY Interrupt status for a given event in the Status 1 (STS1) and Status 2 (STS2) registers, the corresponding mask bit in the Interrupt Mask 1 (IMASK1) and Interrupt Mask 2 (IMSK2) registers must be written to ‘0’ to enable the interrupt. When the associated event occurs setting the status bit, the PHY Interrupt status bit will also be asserted. When the event to negate the status bit is true, or the corresponding bit in the Interrupt Mask Register is set disabling the interrupt, the PHY Interrupt status bit will be deasserted.

All PHY interrupts are disabled (masked) following a reset.