11.2.19 TSU Timer Increment Sub-nanoseconds Register
| Name: | MAC_TISUBN |
| Address: | 0x06F |
| Reset: | 0x00000000 |
| Property: | Read/Write |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| LSBTIR[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | RO | RO | RO | RO | RO | RO | RO | RO | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| MSBTIR[15:8] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| MSBTIR[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bits 31:24 – LSBTIR[7:0] Lower Significant Bits of Timer Increment Register
The least significant bits 16 bits of the sub nanosecond timer increment. This bitfield combines with LMSBTIR to provide a 24-bit timer_increment counter. These 24 bits are the sub-ns value which the TSU timer will be incremented each clock cycle.
Bits 15:0 – MSBTIR[15:0] Most Significant Bits of Timer Increment Register
The most significant bits 16 bits of the sub nanosecond timer increment. This bitfield combines with LSBTIR to provide a 24-bit timer increment counter. These 24 bits are the sub-ns value which the TSU timer will be incremented each clock cycle. Bit n = 2(n-24) ns giving a resolution of approximately 5.86E-17 sec (16 bits give 15.2 femtoseconds).