8.3 Power Connectivity

This section describes typical power configuration for the LAN8650/1 devices with the power supply architecture and recommended decoupling.

The VDDA pins supply power to the internal 3.3V analog circuits while the VDDP pins supply power to the 3.3V digital I/O pins. The internal digital logic of the LAN8650/1 operates at 1.8V. For the LAN8650, this 1.8V is supplied through the VDDC core power pins. The LAN8651 incorporates an internal 1.8V low drop-out regulator that powers the 1.8V core from the 3.3V VDDA analog power.

For applications requiring a low power sleep state and wake-up, an uninterrupted, continuous 3.3V power supply (3.3Vcont) must be connected to VDDAU to power the internal wake-up circuitry and the INH pin. The INH pin will then drive enable pins for the separate switched local power supplies for VDDA, VDDP and, for the LAN8650, VDDC.

In a design where sleep mode is not used, a continuous 3.3V power supply is not necessary and VDDAU is therefore connected to the same 3.3V power supply as VDDA. When VDDAU and VDDA are not connected to the same supply, the VDDA supply pin must never exceed the VDDAU supply pin by more than 0.5V. One approach to satisfying this power sequencing requirement is to connect a Schottky diode between the power supplies to prevent VDDA from exceeding VDDAU by more than a forward-biased voltage drop. The Schottky diode must be sized appropriately if used; the forward voltage drop must be less than 0.5V when the diode conducts current when VDDA exceeds VDDAU.

The LAN8650 has an additional restriction: the VDDC supply pin must never exceed the VDDP supply pin by more than 0.5V. A Schottky diode can also be used, as above, to ensure this requirement is met.

Proper decoupling of the LAN8650/1 power distribution network is a prerequisite for stable operation and best EMC performance. Low ESR 0.1 μF and 0.01 μF capacitors are placed at each of the VDDA, VDDP, and, in the case of the LAN8650, the VDDC pins. These decoupling capacitors should be located right at the pin as close as possible to minimize parasitic inductance and maximize their effectiveness. This is typically done by placing the decoupling capacitors on the opposite side of the board from the device directly under the pin and connecting them to the exposed pad ground. Priority is always given to the placement of the smaller 0.01 μF decoupling capacitor during layout to achieve optimal effectiveness due to its lower capacitance. Each decoupling capacitor is ideally connected to the power plane through two vias to minimize interconnection inductance; decoupling capacitors should not share vias.

In addition to the decoupling capacitors at each pin, a bulk capacitance, typically 10 μF, is placed near the LAN8650/1 in the direction of the power supply that will be supplying current. The bulk capacitors serve to provide low frequency energy that is outside the supply’s response time.

For the LAN8651, a 4.7 μF low ESR (metal film) capacitor is required on the CCOMP pin to provide external capacitive compensation to the internal 1.8V regulator. The addition of 0.1 μF and 0.01 μF decoupling capacitors to the CCOMP pin may be found useful, but are not required.

EMI sensitive applications requiring increased noise performance, may optionally add ferrite beads such as the Würth 742792640 to create localized power islands around the device for the VDDA, VDDAU, and VDDP supplies as illustrated in Figure 8-4 and Figure 8-5. When a ferrite bead is used, it should have a resistance of around 300Ω at 100 MHz. Additionally, the ferrite bead must have a DC current rating at least twice the maximum current to be supplied to the power pins to avoid core saturation and degradation in performance. During the prototype phase, it is recommended to include the option for the ferrite beads should the need arise to populate it to improve noise immunity.

Depending on the properties of the ferrite bead, its combination with the small decoupling capacitors may cause resonant peaking at certain frequencies leading to an undesired amplification of certain frequencies of noise in the system resulting in increased electromagnetic radiation and noise coupling in form of amplitude noise and jitter. Since the ferrite bead selection is highly dependent on the noise in the system, which varies from design to design, the large bulk capacitor, typically 10 μF, is recommended to be placed on the device side of the ferrite bead. When ferrite beads are used, a 10 μF bulk capacitor on the supply side of the ferrite bead is not necessary. See Figure 8-4 and Figure 8-5.

Ideally, the board stackup will contain a large power plane layer adjacent to a ground plane layer. The capacitance between the power and ground planes serve to provide high frequency, low inductance decoupling. When local power islands are used, the islands should be smaller planes underneath the LAN8651, again adjacent to a ground plane to provide high-frequency capacitive decoupling. The use of power tracks are discouraged but, if used, should be as short and wide as possible to minimize sheet resistance and current dependent voltage ripple at the power distribution to the pins.

The analog pins (WAKE_IN, TRXP, TRXN, XTI, and XTO) must never be driven to more than the VDDAU supply. Furthermore, all other digital pins must never be driven to more than the VDDP supply. These requirements are applicable to power-up and power-down as well as normal operating conditions.

The following figures illustrate typical power configurations for the LAN8650/1.