5.1 SPI Format

The LAN8650/1 receives the SPI serial bit clock, SCLK, from the SPI host microcontroller. On the rising edge of SCLK the data is captured, while on the falling edge of SCLK the data will change. The data on SDI and SDO is always transferred most significant bit/byte first.

Figure 5-1. SPI Clock Polarity/Phase Mode

There are two types of SPI transactions, each with a different transaction protocol:

Ethernet MAC Frame data transactions
Control transactions (access to status and control registers)

The CS_N pin must be asserted (driven low) by the SPI host to begin a transaction on SDI and SDO. The CS_N pin is de-asserted (released) by the SPI host when the transaction completes. CS_N must also be de-asserted between different types of transactions (Ethernet data vs Control). Multiple Ethernet data frames may be transmitted under a single CS_N assertion, but CS_N must be toggled and re-asserted again for every Control transaction.