Blocking (BWIF = 165 kHz):
64 dBc at Frequency Offset = 1 MHz and 48 dBc at 225 kHz
High Image Rejection: 55 dB at 315
MHz/433.92 MHz Without Calibration
Supported Data Rate in the Buffered
Mode 0.5 Kbit/s to 80 Kbit/s (120 Kbit/s Non-Return-to-Zero (NRZ))
Supports Pattern-Based Wake-Up and
Start of Frame Identification
Flexible Service Configuration
Concept with On-the-Fly (OTF) Modification (in IDLEMode) of SRAM Service Parameters
(Data Rate, and So On)
Two service configurations
are located in SRAM and can be modified via SPI
Digital Received Signal Strength
Indicator (RSSI) with Very High Relative Accuracy of ±1 dB
Programmable Clock Output Derived
from Crystal Frequency
SPI for Receive (RX) Data Access and
Receiver Configuration
500-Kbit SPI Data Rate for Short
Periods on SPI Bus and Host Controller
Configurable EVENT Signal Indicates
the Status of the IC to an External Microcontroller
Automatic Low-Power Channel Polling
with Flexible Configuration Concerning Timing, Order and Participating Channels
Fast Reaction Time
Supports Mixed ASK/FSK Telegrams
Non-Byte Aligned Data Reception
Supply Voltage Ranges 1.9V to
5.5V
Temperature Range -40°C to
+105°C
Electrostatic Discharge (ESD)
Protection at All Pins (±4 kV HBM, ±200V MM, ±750V FCDM)
Small 5 mm × 5 mm QFN32 Package/Pitch
0.5 mm
Package and Pin-to-Pin Compatibility
with ATA5780N and ATA5781/2/3
Backward RF Matching Compatibility
with ATA5780N and ATA5781/2/3 (RF Redesign Not Needed)
Suitable for Applications Governed by
EN 300 220 and FCC Part 15, Title 47
The online versions of the documents are provided as a courtesy. Verify all content and data in the device’s PDF documentation found on the device product page.