5.13 Power Good

Power Good (PG) is an open-drain output. For asserting a logic-high level, PG requires an external resistor connected to a pull-up voltage, which must not exceed the input voltage.

PG is asserted when the output voltage reaches 93% of its target regulation voltage. PG is deasserted with a typical delay of 50 µs when the output voltage falls below 90% of its target regulation voltage. The PG falling delay acts as a deglitch timer against very short spikes. The PG output is always immediately deasserted when the EN pin is below the power delivery enable threshold. The value of the pull-up resistor must be high enough to limit the PG pin current to below 5 mA.

The PG is also immediately deasserted (with no delay) whenever an undervoltage condition is detected or for a thermal shutdown.