11.1.1 Electrical Parameters Usage

Tables in the following sections define the limiting values for several electrical parameters:

Unless otherwise noted, these values are valid over the junction temperature range defined in Ordering Information. This junction temperature range is referred to as the “applicable T_J range" in the following sections.
Parameters annotated as "Simulation data" are not production-tested. Their limiting values come from simulations run in corner case conditions and were verified by electrical characterization over a limited number of samples. Additionally, the specifications in Digital Peripheral Timings are simulation data, even though they are not annotated as such.
These limits may be affected by the board on which the device is mounted. In particular, noisy supply and ground conditions must be avoided and care must be taken to provide:
- a PCB with a low-impedance ground plane. A single unbroken ground plane is a minimum requirement.
- low-impedance decoupling of the device power supply inputs. A 10 nF to 220 nF Ceramic X7R (or X5R) capacitor placed very close to each power supply input is a minimum requirement. See specific recommendations regarding analog pins or functions in the corresponding sections. To reduce any potential electromagnetic compatibility (EMC) related issues, it is good practice to double this decoupling capacitor whenever possible with a high frequency one, for example one 100 pF (C0G or NP0) per power supply input.
- low impedance power supply decoupling of external components. This recommendation aims at avoiding large current spikes flowing into the PCB ground and power planes.
In addition, although the device is specified with wide operating supply ranges on most of its supply inputs (for example 1.7V to 3.6V), large and fast supply variations may lead to unpredictable device behavior including, but not limited to, out-of-specification operation. Therefore, in addition to maintaining the power supply inputs within their specified range, it is also mandatory to keep the power supply variations within the limits described in Table 11-1 during the device operation.
Finally, the device performances and operating junction temperature are strongly dependent on the thermal performances of the board on which the device is mounted.

Table 11-1. Maximum Power Supply Variations⁽¹⁾
Symbol	Parameter	Conditions	Min	Max	Unit
V_N	Peak-to-peak ripple and noise voltage	Applies to VDDCORE, VDDCPU, VDDIOP0, VDDIOP1, VDDQSPI0, VDDQSPI1, VDDIODDR, VDDSDMMC0, VDDSDMMC1, VDDSDMMC2, VDDGMAC0, VDDGMAC1	–	3	% V_DC⁽²⁾
V_N	Peak-to-peak ripple and noise voltage	Applies to VDDIN33, VBAT, VDDUTMII, VDDLVDS⁽⁵⁾	–	1	% V_DC⁽²⁾
SR	Slewrate of power supply variations	ΔV ≤ 5% V_{DC_MIN}⁽³⁾⁽⁴⁾	–	±50	V/ms
		ΔV < 10% V_{DC_MIN}	–	±10	V/ms
		ΔV ≥ 10% V_{DC_MIN}	–	±1	V/ms

Note:

VDDANA, VDDIN25 and VDDDPHY are not mentioned in this table, as they must be connected to the VDDOUT25 regulator output that fulfills the electrical requirements of these power inputs.
V_DC is the DC value of the power supply.
V_{DC_MIN} is the minimum operating voltage of the supply input as described in Table 11-4.
ΔV is the amplitude of the variation. The slew rate specification applies when the ΔV ≥ V_N.
The peak-to-peak ripple and noise voltage for VDDLVDS can be relaxed to 3% VDC when this segment is not used with the LVDS PHY.

The following examples and figure illustrate this table:

When working with VDDIOP0 = 3.3V, a maximum power supply ripple and noise voltage of 99 mV peak-to-peak (3% of 3.3V) must be respected.
When working with VDDIN33 = 3.3V, a maximum power supply ripple and noise voltage of 33 mV peak-to-peak (1% of 3.3V) must be respected.

Figure 11-1. Maximum Power Supply Variation