3.3.5.16 Changing Between DLL-Off and DLL-On (DDR3)

The following software sequence should be used to switch from DLL-off to DLL-on:

1. Set the DBG1.dis_hif = 1. This prevents further reads/writes being received on the HIF.
2. Set ZQCTL0.dis_auto_zq=1, to disable automatic generation of ZQCS/MPC(ZQ calibration) commands.
3. Set RFSHCTL3.dis_auto_refresh=1, to disable automatic refreshes.
4. Ensure that all commands have been flushed from the UDDRC by polling DBGCAM.wr_data_pipeline_empty, DBGCAM.rd_data_pipeline_empty^(a), DBGCAM.dbg_wr_q_depth, DBGCAM.dbg_lpr_q_depth, DBGCAM.dbg_rd_q_empty, DBGCAM.dbg_wr_q_empty.
   Note:

   1. To make sure the correct value is propagated, registers DBGCAM.wr_data_pipeline_empty and DBGCAM.rd_data_pipeline_empty must be polled at least twice after DBG1.dis_dq is set to 1.
5. Perform an MRS command (using MRCTRL0 and MRCTRL1 registers) to disable RTT_NOM:
   • DDR3: Write ‘0’ to MR1[9], MR1[6] and MR1[2]
6. Put the SDRAM into Self-Refresh mode by setting PWRCTL.selfref_sw = 1.
7. Wait until STAT.operating_mode[1:0]==11 indicating that the UDDRC is in Self-Refresh mode. Ensure transition to self-refresh was due to software by checking that STAT.selfref_type[1:0]=2’b10.
8. Set MSTR.dll_off_mode = 0
9. Set ZQCTL0.dis_srx_zqcl = 1, as the UDDRC does not support ZQCL after self-refresh when enabling DLL-on mode.
10. Change the clock frequency to the desired value.
11. Update any registers which may be required to change for the new frequency. This includes quasi-dynamic and dynamic registers. This includes both UDDRC registers and PHY registers.
12. Exit the self-refresh state by setting PWRCTL.selfref_sw = 0
13. Perform an MRS command (using MRCTRL0 and MRCTRL1 registers) to enable the DLL. The timing of this MRS is automatically handled by the UDDRC.
    • DDR3: Write 0 to MR1[0]
14. Perform an MRS command (using MRCTRL0 and MRCTRL1 registers) to reset the DLL explicitly by writing to MR0, bit A8. The timing of this MRS is automatically handled by the UDDRC.
15. Perform MRS commands as required to re-program timing registers in the SDRAM for the new frequency (in particular, CL, CWL and WR may need to be changed).
16. Re-enable automatic generation of ZQCS/MPC(ZQ calibration) commands, by setting ZQCTL0.dis_auto_zq=0 if they were previously disabled.
17. Re-enable automatic refreshes (RFSHCTL3.dis_auto_refresh = 0) if they have been previously disabled. This must be done if RFSHCTL3.dis_auto_refresh has been set to ‘1’, as all refreshes (including software-driven refreshes) are disabled until this is done.
18. Restore ZQCTL0.dis_srx_zqcl.
19. Write DBG1.dis_hif = 0 to re-enable reads and writes.

Use the following software programming sequence to switch from DLL-on to DLL-off:

1. Set the DBG1.dis_hif = 1. This prevents further reads/writes being received on the HIF.
2. Set ZQCTL0.dis_auto_zq=1, to disable automatic generation of ZQCS/MPC(ZQ calibration) commands
3. Set RFSHCTL3.dis_auto_refresh=1, to disable automatic refreshes.
4. Ensure all commands have been flushed from the UDDRC by polling DBGCAM.wr_data_pipeline_empty, DBGCAM.rd_data_pipeline_empty^(a), DBGCAM.dbg_wr_q_depth, DBGCAM.dbg_lpr_q_depth, DBGCAM.dbg_rd_q_empty, DBGCAM.dbg_wr_q_empty.
   Note:

   1. To make sure the correct value is propagated, registers DBGCAM.wr_data_pipeline_empty and DBGCAM.rd_data_pipeline_empty must be polled at least twice after DBG1.dis_dq is set to 1.
5. Perform an MRS command (using MRCTRL0 and MRCTRL1 registers) to disable RTT_NOM:
   • DDR3: Write ‘0’ to MR1[9], MR1[6] and MR1[2]
6. Perform an MRS command (using MRCTRL0 and MRCTRL1 registers) to write ‘0’ to MR2[10:9], to disable RTT_WR (and therefore disable dynamic ODT). This applies for both DDR3 and DDR4.
7. Perform an MRS command (using MRCTRL0 and MRCTRL1 registers) to disable the DLL. The timing of this MRS is automatically handled by the UDDRC.
   • DDR3: Write ‘1’ to MR1[0]
8. Put the SDRAM into Self-Refresh mode by setting PWRCTL.selfref_sw = 1, and polling STAT.operating_mode to ensure the DDRC has entered self-refresh.
9. Wait until STAT.operating_mode[1:0]==11 indicating that the UDDRC controller is in Self-Refresh mode. Ensure transition to self-refresh was due to software by checking that STAT.selfref_type[1:0]=2’b10.
10. Set the MSTR.dll_off_mode = 1.
11. Change the clock frequency to the desired value.
12. Update any registers which may be required to change for the new frequency. This includes quasi-dynamic and dynamic registers. This includes both UDDRC registers and PHY registers.
13. Exit the Self-Refresh state by setting PWRCTL.selfref_sw = 0.
14. Perform MRS commands as required to re-program timing registers in the SDRAM for the new frequency (in particular, CL, CWL and WR may need to be changed).
15. Re-enable automatic generation of ZQCS/MPC(ZQ calibration) commands, by setting ZQCTL0.dis_auto_zq=0 if they were previously disabled.
16. Re-enable automatic refreshes (RFSHCTL3.dis_auto_refresh = 0) if they have been previously disabled.
17. Restore ZQCTL0.dis_srx_zqcl.
18. Write DBG1.dis_hif = 0 to re-enable reads and writes.