2.2.1 System Bus and Interconnect
The device on-chip interconnect is architectured around the following components:
- 5x AXI matrixes based on the Arm NIC-400 module
- 1x AHB matrix
- 11x APB buses
- 1x Universal DDR Memory Controller (UDDRC)
The following features are supported by the interconnect backbone:
- Quality of Service (QoS) to ensure priorities and limits for all AXI and AHB transactions
- Performance monitoring to track AXI bus activity
| Advanced Peripheral Bus | Master Clock | User Interfaces |
|---|---|---|
| APB0 | MCK0 | SECURAM, SECUMOD, SFRBU, CPKCC, TZPM, PIOA, PMC, SYSC, PUF, CHIPID |
| APB1 | GCLK ADC | ADC |
| MCK1 | XDMAC2, SDMMC[2:0] | |
| MCK3 | LCDC, DSI, LVDSC | |
| MCK6 | GMAC[1:0], XDMAC[1:0], AES, SHA, TDES, TRNG | |
| APB2 | MCK7 | PIT64B[2:0], SSC0, FLEXCOM[3:0], EIC, ACC, PWM, SFR |
| APB3 | MCK8 | TZAESBASC, PIT64B[5:3], SSC1, FLEXCOM[7:4], TC0 |
| APB4 | MCK9 | PDMC[1:0], ASRC, SPDIFRX, SPDIFTX, I2SMCC[1:0], FLEXCOM[10:8] |
| APB5 | MCK6 | TZC |
| APB6 | MCK5 | MCAN[4:0], TC1, MATRIX, SMC, QSPI[1:0], UDPHSA, UDPHSB, ICM, TZAESB, TCPCA, TCPCB |
| APB7 | MCK2 | UDDRC, DDR3PHY |
| APB8 | MCK8 | I3CC |
| APB9 | MCK6 | Secure Debug |
| APB10 | MCK6 | Debug |