2.2.1 System Bus and Interconnect

The device on-chip interconnect is architectured around the following components:

  • 5x AXI matrixes based on the Arm NIC-400 module
  • 1x AHB matrix
  • 11x APB buses
  • 1x Universal DDR Memory Controller (UDDRC)

The following features are supported by the interconnect backbone:

  • Quality of Service (QoS) to ensure priorities and limits for all AXI and AHB transactions
  • Performance monitoring to track AXI bus activity
Table 2-2. Advanced Peripheral Bus User Interfaces
Advanced Peripheral BusMaster ClockUser Interfaces
APB0MCK0SECURAM, SECUMOD, SFRBU, CPKCC, TZPM, PIOA, PMC, SYSC, PUF, CHIPID
APB1GCLK ADCADC
MCK1XDMAC2, SDMMC[2:0]
MCK3LCDC, DSI, LVDSC
MCK6GMAC[1:0], XDMAC[1:0], AES, SHA, TDES, TRNG
APB2MCK7PIT64B[2:0], SSC0, FLEXCOM[3:0], EIC, ACC, PWM, SFR
APB3MCK8TZAESBASC, PIT64B[5:3], SSC1, FLEXCOM[7:4], TC0
APB4MCK9PDMC[1:0], ASRC, SPDIFRX, SPDIFTX, I2SMCC[1:0], FLEXCOM[10:8]
APB5MCK6TZC
APB6MCK5MCAN[4:0], TC1, MATRIX, SMC, QSPI[1:0], UDPHSA, UDPHSB, ICM, TZAESB, TCPCA, TCPCB
APB7MCK2UDDRC, DDR3PHY
APB8MCK8I3CC
APB9MCK6Secure Debug
APB10MCK6Debug