7.2.7.3 I2SMCC Mode Register B

This register can only be written if WPCFEN is cleared in the Inter-IC Sound Write Protection Mode Register.

The I2SMCC_MRB must only be written when the I2SMCC is stopped in order to avoid unexpected behavior on the I2SMCC_WS, I2SMCC_CK and I2SMCC_DOUT outputs. The proper sequence is to write to I2SMCC_MRB, then write to I2SMCC_CR to enable the I2SMCC or to disable the I2SMCC before writing a new value to I2SMCC_MRB.

Name:	I2SMCC_MRB
Offset:	0x08
Reset:	0x03000000
Property:	Read/Write


Bit	31	30	29	28	27	26	25	24
	DTCEN7	DTCEN6	DTCEN5	DTCEN4	DTCEN3	DTCEN2	DTCEN1	DTCEN0
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	1	1


Bit	23	22	21	20	19	18	17	16
		I2SLINESIZE[2:0]
Access		R/W	R/W	R/W
Reset		0	0	0


Bit	15	14	13	12	11	10	9	8
							DMACHUNK[1:0]
Access							R/W	R/W
Reset							0	0


Bit	7	6	5	4	3	2	1	0
		PACK24	LEFTAL24	FIFOEN		TXDIRECT	RXDIRECT	CRAMODE
Access		R/W	R/W	R/W		R/W	R/W	R/W
Reset		0	0	0		0	0	0

Bits 24, 25, 26, 27, 28, 29, 30, 31 – DTCENx Direct Audio Transmit Channel x Enable

The receiver does not provide the capability to select the channels that will be transferred on the direct link to ASRC. The selection is possible in the ASRC.

Value	Description
0	The channel x from the direct audio stream is not transmitted on I²S line.
1	The channel x from the direct audio stream is transmitted on I²S line.

Bits 22:20 – I2SLINESIZE[2:0] I²S Transceiver Data Slot Size Selection

Value	Name	Description
0	DATALENGTH_DEFINED	The I²S data slot size is configured by I2SMCC_MRA.DATALENGTH and the software is forced to manage audio samples of the same size as the ones transferred on I²S line.
1	32_BITS	The I²S data slot size is 32-bit. I2SMCC_MRA.DATALENGTH/IWS has no effect on I2S data slot size but defines the audio sample size managed at user interface level.
2	32_24_BITS	The I²S data slot size is 24-bit or 32-bit. 32 or 24 bits depends on I2SMCC_MR.IWS. I2SMCC_MRA.DATALENGTH/IWS have no effect on I2S data slot size but define the audio sample size managed at user interface level.
3	16_BITS	The I²S data slot size is 16-bit. I2SMCC_MRA.DATALENGTH/IWS have no effect on I²S data slot size but defines the audio sample size managed at user interface level.
4	8_BITS	The I²S data slot size is 8-bit. I2SMCC_MRA.DATALENGTH/IWS have no effect on I²S data slot size but defines the audio sample size managed at user interface level.

Bits 9:8 – DMACHUNK[1:0] DMA Chunk Size

Value	Name	Description
0	1_WORD	A DMA transfer request is issued when at least 1 word is empty in the FIFO.
1	2_WORDS	A DMA transfer request is issued when at least 2 words are empty in the FIFO. When PACK24=1, only 1-word chunks are allowed for the DMA transfer.
2	4_WORDS	A DMA transfer request is issued when at least 4 words are empty in the FIFO. Limitations exist when operating in Mono or TDM. See TX DMA Chunk Configurations and RX DMA Chunk Configurations. When PACK24=1, only 1-word chunks are allowed for the DMA transfer.
3	8_WORDS	A DMA transfer request is issued when at least 8 words are empty in the FIFO. Limitations exist when operating in Mono or TDM. See TX DMA Chunk Configurations and RX DMA Chunk Configurations. When PACK24=1, only 1-word chunks are allowed for the DMA transfer.

Bit 6 – PACK24 Packed 24-bit Mode

When PACK24=1, the DMA chunk size is limited to 1 word.

Value	Description
0	Each 24-bit audio sample is mapped into the 32-bit Holding register.
1	24-bit audio samples are compacted in the 32-bit Holding register to optimize data transfer in system bus and memory. The FIFO must be enabled (I2SMCC_MRB.FIFOEN = 1).

Bit 5 – LEFTAL24 Left-Aligned 24-bit Data

Value	Description
0	The 24-bit audio sample is right-aligned in the 32-bit Holding register.
1	The 24-bit audio sample is left-aligned in the 32-bit Holding register.

Bit 4 – FIFOEN FIFO Enable

Value	Description
0	The Receive and Transmit FIFOs are disabled.
1	The Receive and Transmit FIFOs are enabled. Transmit data can only be written through I2SMCC_THR. Receive data can only be read through I2SMCC_RHR.

Bit 2 – TXDIRECT Receiver Direct Access Enable

Value	Description
0	The I2SMCC_THR must be loaded by software or DMA to transfer audio sample on I²S line.
1	Audio Sample Rate Converter (ASRC) can directly transmit the converted audio samples on I²S line without software or DMA intervention. The FIFO must be enabled (I2SMCC_MRB.FIFOEN = 1).

Bit 1 – RXDIRECT Receiver Direct Access Enable

Value	Description
0	The I2SMCC_RHR must be read by software or DMA to read audio samples from I²S line.
1	Audio Sample Rate Converter (ASRC) can be directly loaded with the audio samples recovered from I²S line without software or DMA intervention. The FIFO must be enabled (I2SMCC_MRB.FIFOEN = 1).

Bit 0 – CRAMODE Common Register Access Mode

Value	Name	Description
0	LEFT_FIRST	All enabled I²S left channels are filled first, then I²S right channels.
1	REGULAR	An enabled I²S left channel is filled, then the corresponding right channel, until all channels are filled.