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Up to 1-GHz Arm® Cortex®-A7, MIPI/LVDS Display, Dual Gigabit Ethernet, Audio and Security
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Product Pages
SAMA7D65
Home
2
CPU and Interconnect
2.7
Bus Matrix (MATRIX)
Introduction
Reference Document
1
Overview
2
CPU and Interconnect
2.1
Event System
2.2
System Interconnect and Security (SIS)
2.3
Cortex-A7 Processor (Arm)
2.4
External Interrupt Controller (EIC)
2.5
Debug and Test
2.6
NIC-400 Global Programmer’s View (NICGPV)
2.7
Bus Matrix (MATRIX)
2.7.1
Description
2.7.2
Embedded Characteristics
2.7.3
Memory Mapping
2.7.4
Special Bus Granting Techniques
2.7.5
No Default Host
2.7.6
Last Access Host
2.7.7
Fixed Default Host
2.7.8
Arbitration
2.7.9
Register Write Protection
2.7.10
TrustZone Extension
2.7.11
Register Summary
2.8
DMA Controller (XDMAC)
2.9
Boot Strategies
3
Memories
4
System Controller
5
Analog Subsystem
6
Image Subsystem
7
Audio Subsystem
8
Security and Cryptography Subsystem
9
Connectivity Subsystem
10
USB Subsystem
11
Electrical and Mechanical Characteristics
12
Glossary
13
Revision History
Microchip Information
2.7 Bus Matrix (MATRIX)
