8.12.7.11 SECUMOD JTAG Protection Control Register

Note: Reset value is:

0x00000001 when fuse DEFDBG is programmed.
0x00000009 when fuse DEFDBG is not programmed.

Name:	SECUMOD_JTAGCR
Offset:	0x0070
Reset:	see Note
Property:	Read/Write


Bit	31	30	29	28	27	26	25	24

Access
Reset


Bit	23	22	21	20	19	18	17	16

Access
Reset


Bit	15	14	13	12	11	10	9	8
								FNTRST_BSD
Access								R/W
Reset


Bit	7	6	5	4	3	2	1	0
				PROC_DEBUG_MON	PROC_DEBUG_MODE[2:0]			FNTRST_DEBUG
Access				R/W	R/W	R/W	R/W	R/W
Reset

Bit 8 – FNTRST_BSD Force Boundary JTAG NTRST

Value	Description
0	Boundary JTAG are not blocked by the SECUMOD.
1	Boundary JTAG reset are held low, preventing Boundary JTAG to work.

Bit 4 – PROC_DEBUG_MON Debug Acknowledge (DBGACK) Monitoring

Value	Description
0	The Arm processor pin DBGACK is not monitored; as a consequence, the software can access debug features of the processor without causing an intrusion in the SECUMOD.
1	The Arm processor pin DBGACK is monitored. Processor entering in Debug mode triggers an intrusion.

Bits 3:1 – PROC_DEBUG_MODE[2:0] Invasive/Non-Invasive Secure/Non-Secure Debug Permissions

This field is used to set different debug permission levels. For instance, it can be used to prevent debug on secure parts of the code. The table below shows the effect of the field value on the processor pins (SPIDEN, DBGEN, SPNIDEN and NIDEN).


PROC_DEBUG_MODE Value	Debug Permissions	SPIDEN	DBGEN	SPNIDEN	NIDEN
b000	No Debug	0	0	0	0
b001	Non-Invasive, Non-Secure	0	0	0	1
b010	Full Non-Secure (Invasive and Non-Invasive)	0	1	0	0
b011	Full Non-Secure + Non-Invasive Secure	0	1	1	1
b100	Full Debug allowed	1	1	1	1

Bit 0 – FNTRST_DEBUG Force ARM Processor’s TAP NTRST

Value	Description
0	The ARM processor’s TAP controller access is not blocked by the SECUMOD.
1	nDBGRESET of the ARM processor’s TAP controller is held low, preventing the processor to switch to Debug state.