11.1.7.12 Pulse Density Microphone Controller (PDMC)

Timings are provided in the following domains:

1.8V domain: VDDIO from 1.7V to 1.9V, maximum external capacitor = 10 pF, DRV= 1, SR = 1
3.3V domain: VDDIO from 3.0V to 3.6V, maximum external capacitor = 10 pF, DRV= 0, SR = 1

Figure 11-39. PDMC Timing Diagram


Symbol	Parameter	Conditions	Min	Max	Unit
f_{PDM_CLK}	PDM clock frequency	–		5	MHz
ẟ_{PDM_CLK}	PDM clock duty cycle	–	48	52	%
t_SU	Data input setup time	–	20	–	ns
t_HLD	Data input hold time	–	0	–	ns