11.1.8.11 PLL Characteristics

The following characteristics apply to CPUPLL, DDRPLL, IMGPLL, SYSPLL, BAUDPLL, AUDIOPLL, GPUPLL, LVDSPLL and ETHPLL and are provided for register PMC_PLL_ACR programmed to the recommended value 0x00070010. For USBPLL, see note (5).

Table 11-57. PLL Characteristics
Symbol	Parameter	Conditions	Min	Max	Unit
V_DDIN33	Supply voltage range (VDDIN33)⁽¹⁾	–	3.0	3.6	V
V_DDCORE	Supply voltage range (VDDCORE)	–	1.03	1.21	V
I_VDDIN33	Current consumption (VDDIN33)⁽²⁾	f_COREPLLCK = 1.0 GHz	–	2.9	mA
I_VDDCORE	Current consumption (VDDCORE)⁽²⁾	f_COREPLLCK = 1.0 GHz	–	3.5	mA
t_START	Start-up time⁽²⁾	To reach 95% of target frequency	–	50⁽³⁾	μs
f_IN	Input frequency range	–	10	50	MHz
f_COREPLLCK	COREPLLCK frequency range	–	600	1200	MHz
f_IOPLLCK	IOPLLCK⁽⁴⁾ frequency range	–	–	100	MHz

Note:

The PLLs are powered by the 2.5V regulated output, which is supplied from VDDIN33.
Simulation data
For USBPLL, t_{START_MAX} = 150 µs
IOPLLCK is available on the AUDIOPLL only and corresponds to the AUDIOCLK pin.
For optimal setting of the USBPLL, set PMC_PLL_ACR as follows:
PMC_PLL_ACR = 0x09023010 for f_IN = [12 MHz, 18 MHz]
PMC_PLL_ACR = 0x12023010 for f_IN = [18 MHz, 32 MHz]
PMC_PLL_ACR = 0x1B023010 for f_IN = [32 MHz, 48 MHz]

Table 11-58. PLL Output Clocks Characteristics
Symbol	Parameter⁽¹⁾	Conditions	Min	Max	Unit
f_CPUPLLCK	CPUPLLCK frequency range	–	–	1000	MHz
f_DDRPLLCK	DDRPLLCK frequency range	–	–	533	MHz
f_GPUPLLCK	GPUPLLCK frequency range	–	–	533	MHz
f_SYSPLLCK	SYSPLLCK frequency range	–	–	416	MHz
f_BAUDPLLCK	BAUDPLLCK frequency range	–	–	300	MHz
f_AUDIOPLLCK	AUDIOPLLCK frequency range	–	–	300	MHz
f_ETHPLLCK	ETHPLLCK frequency range	–	–	250	MHz
f_USBPLLCK	USBPLLCK frequency range	–	–	480	MHz
f_LVDSPLLCK	LVDSPLLCK frequency range	–	–	630	MHz

Note:

Simulation data

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