11.1.7.8 LCD Controller (LCDC)

Timings are provided in the following conditions:

1.8V domain: VDDIO from 1.7V to 1.9V, maximum external capacitor = 10 pF, DRV = 1, SR = 1
3.3V domain: VDDIO from 3.0V to 3.6V, maximum external capacitor = 10 pF, DRV = 0, SR = 1

Figure 11-26. LCD Timings

Table 11-34. LCDC Timings
Symbol	Parameter	Conditions	Min	Max	Unit
f_{LCDC_PCK}	Maximum LCDC_PCK clock frequency	–	–	90	MHz
t_VALID	Clock to LCDC_DATx valid output	–	–	3.3	ns