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Up to 1-GHz Arm® Cortex®-A7, MIPI/LVDS Display, Dual Gigabit Ethernet, Audio and Security
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SAMA7D65
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3
Memories
3.4
DDR/LPDDR Physical Interface (DDR3PHY)
Introduction
Reference Document
1
Overview
2
CPU and Interconnect
3
Memories
3.1
Overview
3.2
Static Memory Controller (SMC)
3.3
Universal DDR Memory Controller (UDDRC)
3.4
DDR/LPDDR Physical Interface (DDR3PHY)
3.4.1
Description
3.4.2
Embedded Characteristics
3.4.3
Functional Description
3.4.4
Register Summary
4
System Controller
5
Analog Subsystem
6
Image Subsystem
7
Audio Subsystem
8
Security and Cryptography Subsystem
9
Connectivity Subsystem
10
USB Subsystem
11
Electrical and Mechanical Characteristics
12
Glossary
13
Revision History
Microchip Information
3.4 DDR/LPDDR Physical Interface (DDR3PHY)
