1.7 Signal Description
| Signal Name | Function | Type | Comments | Active Level |
|---|---|---|---|---|
| Clocks, Oscillators and PLLs | ||||
| XIN | Main Oscillator Input | Input | – | – |
| XOUT | Main Oscillator Output | Output | – | – |
| XIN32 | Slow Clock Oscillator Input | Input | – | – |
| XOUT32 | Slow Clock Oscillator Output | Output | – | – |
| AUDIOCLK | Audio Clock | Output | – | – |
| PCK[7:0] | Programmable Clock Output | Output | Reset State: | – |
| - PIO Input | ||||
| - Internal Pull-up enabled | ||||
| - Schmitt Trigger enabled | ||||
| Shutdown, Wake-up Logic | ||||
| LPM | Low-power Mode | Output | – | – |
| SHDN | Shutdown Control | Output | – | – |
| WKUP[5:0] | Wakeup Input | Input | – | – |
| ICE and JTAG | ||||
| TCK/SWCLK | Test Clock/Serial Wire Clock | Input | – | – |
| TDI | Test Data In | Input | – | – |
| TDO | Test Data Out | Output | – | – |
| TMS/SWDIO | Test Mode Select/Serial Wire Input/Output | I/O | – | – |
| JTAGSEL | JTAG Selection | Input | – | – |
| Reset/Test | ||||
| NRST | Microprocessor Reset | Input | – | Low |
| TST | Test Mode Select | Input | – | – |
| NTRST | Test Reset Signal | Input | – | – |
| NRST_OUT | Microprocessor Reset Output | Output | – | Low |
| External Interrupt Controller – EIC | ||||
| IRQ[1:0] | External Interrupt Input | Input | – | – |
| PIO Controller – PIO | ||||
| PA[31:0] | Parallel IO Controller | I/O | – | – |
| PB[31:0] | Parallel IO Controller | I/O | – | – |
| PC[31:0] | Parallel IO Controller | I/O | – | – |
| PD[31:0] | Parallel IO Controller | I/O | – | – |
| PE[13:0] | Parallel IO Controller | I/O | – | – |
| External Bus Interface – EBI | ||||
| D[15:0] | Data Bus | I/O | – | – |
| A22/A21/A[12:0] | Address Bus | Output | – | – |
| NWAIT | External Wait Signal | Input | – | Low |
| Static Memory Controller – SMC | ||||
| NCS0/NANDCS0 | Chip Select Lines | Output | – | Low |
| NCS1/NANDCS1 | ||||
| NWR[1:0] | Write Signal | Output | – | Low |
| NRD | Read Signal | Output | – | Low |
| NWE | Write Enable Signal | Output | – | Low |
| NBS[1:0] | Byte Select Signal | Output | – | Low |
| NANDOE | NAND Flash Output Enable | Output | – | Low |
| NANDWE | NAND Flash Write Enable | Output | – | Low |
| SMCK | Clock for synchronous transfer | Output | – | – |
| Universal DDR Memory Controller – UDDRC | ||||
| DDR_CLK, DDR_CLKN | Differential Clock | Output | – | – |
| DDR_CKE | Clock Enable | Output | – | High |
| DDR_CSN | Chip Select | Output | – | Low |
| DDR_BA[2:0] | Bank Select | Output | – | Low |
| DDR_WEN | Write Enable | Output | – | Low |
| DDR_RASN, DDR_CASN | Row Signal, Column Signal | Output | – | Low |
| DDR_A[15:0] | Address Bus | Output | – | – |
| DDR_D[15:0] | Data Bus | I/O | – | – |
|
DDR_DQS[1:0], | Differential Data Strobe | I/O | – | – |
| DDR_DQM[1:0] | Write Data Mask | Output | – | – |
| DDR_ZQ | Calibration Reference | Input | – | – |
| DDR_VREF | Reference Voltage | Input | – | – |
| DDR_RESETN | DDR3 Active Low Asynchronous Reset | Output | – | Low |
| DDR_ODT | On-Die Termination | Output | – | High |
| Secure Digital MultiMedia Card Controller – SDMMC[2:0] | ||||
| SDMMC[2:0]_CAL | SD Card Calibration | Input | – | Low |
| SDMMC[2:0]_CD | SD Card/e.MMC Card Detect | Input | – | Low |
| SDMMC[2:0]_CMD | SD Card/e.MMC Command/Response Line | I/O | – | – |
| SDMMC[2:0]_WP | SD Card Connector Write Protect Signal | Input | – | High |
| SDMMC[1:0]_RSTN | e.MMC Reset Signal | Output | – | Low |
| SDMMC[2:0]_1V8SEL | SD Card Signal Voltage Selection | Output | – | – |
| SDMMC[2:0]_CK | SD Card/e.MMC Clock Signal | Output | – | – |
| SDMMC[2:1]_DAT[3:0] | SD Card Data Lines | I/O | – | – |
| SDMMC0_DAT[7:0] | e.MMC Data Lines | I/O | – | – |
| SDMMC0_DS | e.MMC Data Strobe | Input | – | – |
| I3C Controller – I3CC | ||||
| I3CC_SCL | Serial Clock | I/O | – | – |
| I3CC_SDA | Serial Data | I/O | – | – |
| I3CC_SDASPUE | Serial Data Pull-up Enable | Output | – | – |
| Flexible Serial Communication Controller – FLEXCOM[10:0] | ||||
| FLEXCOM[10:0]_IO0 | Transmit Data | I/O | – | – |
| FLEXCOM[10:0]_IO1 | Receive Data | I/O | – | – |
| FLEXCOM[10:0]_IO2 | Serial Clock | I/O | – | – |
| FLEXCOM[10:0]_IO3 | Clear To Send/SPI Chip Select 0 | I/O | – | – |
| FLEXCOM[10:0]_IO4 | Request To Send/SPI Chip Select 1 | Output | – | – |
| FLEXCOM[10:0]_IO5 | SPI Chip Select 2 | Output | – | – |
| FLEXCOM[10:0]_IO6 | SPI Chip Select 3 | Output | – | – |
| Inter-IC Sound Multi Channel Controller – I2SMCC[1:0] | ||||
| I2SMCC[1:0]_MCK | Bus Clock | Output | – | – |
| I2SMCC[1:0]_CK | Serial Clock | I/O | – | – |
| I2SMCC[1:0]_WS | Word Select | I/O | – | – |
| I2SMCC[1:0]_DIN[3:0] | Serial Data Input | Input | – | – |
| I2SMCC[1:0]_DOUT[3:0] | Serial Data Output | Output | – | – |
| Synchronous Serial Controller – SSC[1:0] | ||||
| TD[1:0] | Transmit Data | Output | – | – |
| RD[1:0] | Receive Data | Input | – | – |
| TK[1:0] | Transmit Clock | I/O | – | – |
| RK[1:0] | Receive Clock | I/O | – | – |
| TF[1:0] | Transmit Frame Sync | I/O | – | – |
| RF[1:0] | Receive Frame Sync | I/O | – | – |
| Timer Counter – TC[1:0] | ||||
| TCLK[5:0] | External Clock Input | Input | – | – |
| TIOA[5:0] | I/O Line A | I/O | – | – |
| TIOB[5:0] | I/O Line B | I/O | – | – |
| Quad/Octal IO SPI – QSPI[1:0] | ||||
| QSPI[1:0]_SCK | Serial Clock | Output | – | – |
| QSPI[1:0]_CS | Chip Select | Output | – | Low |
| QSPI[1:0]_IO[3:0] | QSPI I/O | I/O | – | – |
| QIO0 is QMOSI Host Out - Client In | ||||
| QIO1 is QMISO Host In - Client Out | ||||
| QSPI0_IO[7:4] | QSPI0 I/Os for Octal Mode | I/O | – | – |
| QSPI0_SCKN | Negative QSPI0 Serial Clock | Output | – | – |
| QSPI0_INT | QSPI0 Interrupt | Input | – | Low |
| QSPI0_DQS | QSPI0 Data Strobe | Input | – | – |
| Pulse Width Modulation Controller – PWM | ||||
| PWMH[3:0] | Waveform Output High | Output | – | – |
| PWML[3:0] | Waveform Output Low | Output | – | – |
| PWMFI[1:0] | Fault Inputs | Input | – | – |
| PWMEXTRG[1:0] | External Trigger | Input | – | – |
| USB High Speed Ports A, B, C | ||||
| HHSDPA |
Host Port A High Speed Data + | Analog | – | – |
| HHSDMA |
Host Port A High Speed Data - | Analog | – | – |
| HHSDPB |
Host Port B High Speed Data + | Analog | – | – |
| HHSDMB |
Host Port B High Speed Data - | Analog | – | – |
| HHSDPC | Host Port C High Speed Data + | Analog | – | – |
| HHSDMC | Host Port C High Speed Data - | Analog | – | – |
| HHSA_CC[2:1] | Host Port A Configuration Channel 1 and 2 | Analog | Multiplexed with PIO | – |
| HHSB_CC[2:1] | Host Port B Configuration Channel 1 and 2 | Analog | Multiplexed with PIO | – |
| HHSRTUNE | Host Tune Resistor | Analog | – | – |
| Gigabit Ethernet MAC 10/100/1000 – GMAC[1:0] | ||||
| G[1:0]_TXEN/G[1:0]_TXCTL | Transmit Enable or Transmit Control Signal | Output | – | – |
| G[1:0]_TX[3:0] | Transmit Data | Output | – | – |
| G[1:0]_TSUCOMP | TSU Timer Comparison Valid | Output | – | – |
| G[1:0]_REFCK/G[1:0]_TXCK | Transmit Clock or 50 MHz Reference Clock | I/O | – | – |
| G[1:0]_RX[3:0] | Receive Data | Input | – | – |
| G[1:0]_RXCTL/G[1:0]_CRSDV | Receive Data Valid or Carrier Sense and Data Valid or Receive Control Signal | Input | – | – |
| G[1:0]_RXCK | Receive Clock | Input | – | – |
| G[1:0]_RXER | Receive Error | Input | – | – |
| G[1:0]_MDC | Management Data Clock | Output | – | – |
| G[1:0]_MDIO | Management Data Input/Output | I/O | – | – |
| Analog-to-Digital Converter – ADC | ||||
| AD[0:15] | Analog Inputs | Analog | – | – |
| ADTRG | ADC Trigger | Input | – | – |
| ADVREFP | ADC Reference | Analog | – | – |
| Analog Comparator Controller – ACC | ||||
| ACCINN[3:1] | External Analog Data Input | Analog | – | – |
| ACCINP[3:0] | External Analog Data Input | Analog | – | – |
| VBG | Internal Bandgap Voltage | Analog | – | – |
| Security Module – SECUMOD | ||||
| PIOBU[3:0] | Tamper I/Os | I/O | – | – |
| Pulse Density Microphone Controller – PDMC[1:0] | ||||
| PDMC[1:0]_DS[1:0] | Data Input | Input | – | – |
| PDMC[1:0]_CLK | Clock Output | Output | – | – |
| Sony/Philips Digital Interface Receiver – SPDIFRX | ||||
| SPDIF_RX | Receive Data | Input | – | – |
| Sony/Philips Digital Interface Transmitter – SPDIFTX | ||||
| SPDIF_TX | Transmit Data | Output | – | – |
| Controller Area Network – MCAN[4:0] | ||||
| CANRX[4:0] | Receive | Input | – | – |
| CANTX[4:0] | Transmit | Output | – | – |
| Low Voltage Differential Signaling Controller – LVDSC | ||||
| LVDS_A[3:0]P | Differential LVDS Data [3:0] Line Transceiver Output | Output | Multiplexed with PIO | – |
| LVDS_A[3:0]M | ||||
| LVDS_CLK1M | Differential LVDS Clock Line Transceiver Output | Output | Multiplexed with PIO | – |
| LVDS_CLK1P | ||||
| LCD Controller – LCDC | ||||
| LCDC_DAT[7:0] | Data Bus Output | Output | – | – |
| LCDC_PCK | Pixel Clock | Output | – | – |
| LCDC_HSYNC | Horizontal Synchronization | Output | – | – |
| LCDC_VSYNC | Vertical Synchronization | Output | – | – |
| LCDC_DEN | Data Enable | Output | – | – |
| LCDC_DISP | Display ON/OFF | Output | ||
| LCDC_PWM | PWM for Contrast Control | Output | – | – |
| MIPI D-PHY | ||||
| MIPI_DP[3:0]/ MIPI_DN[3:0] | MIPI D-PHY Differential Output Data Lane [3:0] | Output | – | – |
| MIPI_CLKP/MIPI_CLKN | MIPI D-PHY Differential Output Clock Lane | Output | – | – |
| MIPI_REXT | Calibration Reference Resistor (4.02 KΩ E96 ) | Input | – | – |