2.9.6.1 Clock Settings

The table below provides clock frequencies configured by the ROM code during boot.

Table 2-37. Clock Frequencies
ClockFrequencyDuring Boot SequenceDuring Monitor ModeDuring Bootstrap Execution
SYS_CLK 378 MHz✔✔✔
CPU_CLK570 MHz✔✔✔
MCK0190 MHz✔✔✔
MCK1189 MHz✔✔✔
MCK5189 MHz✔✔✔
MCK6189 MHz✔✔✔
MCK794.5 MHz✔✔✔
MCK894.5 MHz✔✔✔
MCK994.5 MHz✔✔✔
SDMMC (MCK1) (if the ROM code tries to boot on that interface)189 MHz✔✘✘
QSPI (SYS_CLK / 4) (if the ROM code tries to boot on that interface)

94.5 MHz

(baud rate = 32 MHz)

✔✘✘
NAND NFC (MCK5) (if the ROM code tries to boot on that interface)189 MHz✔✘✘
SPI FLEXCOM (MCK7 or MCK8 or MCK9) (if the ROM code tries to boot on that interface)

94.5 MHz

(baud rate = 12 MHz)

✔✘✘
UTMI (USB PLL CLK) (if an external crystal is supported and the ROM code enters Monitor mode)480 MHz✘✔✘