4.1.3.1 Clocks

All system controller peripherals, except PIT64B[5:0], are part of the CPU System and Security (CSS) matrix that runs on MCK0.

Note: The MCK0 frequency is directly related to the CPU clock, so any change on the CPU clock impacts MCK0.

The system controller peripherals are always on, except:

Parallel Input/Output Controllers (PIOs) that have one clock control (PIOA) for all PIO controllers, clocked with MCK0.
Special Function Registers (SFR).

PIT64B[5:0] are located on the APB Client (APS) matrix, with PIT64B[2:0] clocked with MCK7 and PIT64B[5:3] clocked with MCK8.

In addition, PIT64B[5:0] feature a GCLK input for flexibility. CA7 Base Time (GCLK ID28), defined as MAINCK, is automatically started at reset.