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Up to 1-GHz Arm® Cortex®-A7, MIPI/LVDS Display, Dual Gigabit Ethernet, Audio and Security
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SAMA7D65
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2
CPU and Interconnect
2.4
External Interrupt Controller (EIC)
Introduction
Reference Document
1
Overview
2
CPU and Interconnect
2.1
Event System
2.2
System Interconnect and Security (SIS)
2.3
Cortex-A7 Processor (Arm)
2.4
External Interrupt Controller (EIC)
2.4.1
Description
2.4.2
Embedded Characteristics
2.4.3
Block Diagram
2.4.4
I/O Lines Description
2.4.5
Product Dependencies
2.4.6
Functional Description
2.4.7
Register Summary
2.5
Debug and Test
2.6
NIC-400 Global Programmer’s View (NICGPV)
2.7
Bus Matrix (MATRIX)
2.8
DMA Controller (XDMAC)
2.9
Boot Strategies
3
Memories
4
System Controller
5
Analog Subsystem
6
Image Subsystem
7
Audio Subsystem
8
Security and Cryptography Subsystem
9
Connectivity Subsystem
10
USB Subsystem
11
Electrical and Mechanical Characteristics
12
Glossary
13
Revision History
Microchip Information
2.4 External Interrupt Controller (EIC)
