1.2.2 Enabling the FOSC Fail-Safe Clock Monitor Alongside the Primary or Secondary Oscillator Clock Monitor Causes Issues with Sleep
When the FOSC Fail-Safe Clock Monitor is enabled (FCMEN Configuration bit = 1)
and either the Primary or Secondary Fail-Safe Clock Monitor is also enabled (FCMENS
and/or FCMENP = 1), putting the device to Sleep will cause a Fail-Safe
condition to trigger. This has the effect of erroneously triggering Fail-Safe interrupts
when there has not been a clock interruption. This can also cause the Watchdog Timer to
not properly wake up the part from Sleep.
Work around
If proper functionality in Sleep is required, do not enable the Primary or Secondary Fail-Safe Clock Monitor while the FOSC Fail-Safe Clock Monitor is enabled. If Primary or Secondary Clock Monitoring in Sleep is desired, disable the FOSC Fail-Safe Clock Monitor before the device goes to Sleep.
Affected Silicon Revisions
| A4 | A5 | A6 | B1 |
| X |