1.2.3 Maximum Clock Frequency for EC Mode Is 32 MHz for VDD < 2.0V
When configured in External Clock High-Power (ECH) mode and operating at VDD < 2.0V, the maximum input clock frequency is 32 MHz.
Work around
To obtain a system clock frequency of 64 MHz in ECH mode at VDD < 2.0V,
use a 16 MHz external clock in conjunction with the 4x Phase-Locked Loop (PLL)
circuit (i.e., either RSTOSC Configuration bits = 0b010 or
OSCCON1bits.NOSC = 0b010).
Affected Silicon Revisions
| A4 | A5 | A6 | B1 |
| X |