1.13 MPU Cache Coherency
This example shows how to maintain cache coherency by allocating DMA buffers in non-cacheable SRAM region defined by MPU.
Description
This application performs UART transfer with DMA. One DMA channel is used to receive 10 bytes of data from the UART and another DMA channel is used to echo back the received bytes.
Downloading and Building the Application
To clone or download this application from Github, go to the main page of this repository and then click Clone button to clone this repository or download as zip file. This content can also be downloaded using content manager by following these instructions.
Path of the application within the repository is apps/mpu/mpu_coherent_region/firmware.
To build the application, refer to the following table and open the project using its IDE.
| Project Name | Description |
|---|---|
| pic32cz_ca70_curiosity_ultra.X | MPLABX project for PIC32CZ CA70 Curiosity Ultra Development Kit |
Setting Up the Hardware
The following table shows the target hardware for the application projects.
| Project Name | Description |
|---|---|
| pic32cz_ca70_curiosity_ultra.X | PIC32CZ CA70 Curiosity Ultra Development Kit |
Setting Up PIC32CZ CA70 Ultra Curiosity Development Kit
- Connect the Debug USB port on the board to the computer using a micro USB cable
Running the Application
- Open the Terminal application (Ex.:Tera term) on the computer
- Connect to the PICkit4 On Board
Virtual COM port and configure the serial settings as follows:
- Baud : 115200
- Data : 8 Bits
- Parity : None
- Stop : 1 Bit
- Flow Control : None
- Build and Program the application using its IDE
- The console displays the following message
- Type 10 characters in the terminal. It will echo back the received bytes and toggles the LED
- The following table provides the LED name:
Board LED Name PIC32CZ CA70 Curiosity Ultra Development Kit LED0