31.5.10 ADACQ

ADC Acquisition Time Control Register

Note: The individual bytes in this multibyte register can be accessed with the following register names:

ADACQH: Accesses the high byte ADACQ[12:8]
ADACQL: Accesses the low byte ADACQ[7:0]

Name:	ADACQ
Offset:	0x1D21


Bit	15	14	13	12	11	10	9	8
				ACQ[12:8]
Access				R/W	R/W	R/W	R/W	R/W
Reset				0	0	0	0	0


Bit	7	6	5	4	3	2	1	0
	ACQ[7:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0

Bits 12:0 – ACQ[12:0] Acquisition (charge share time) Select

Table 31-8. Acquisition Time
ADACQ	Acquisition Time
ADACQ	CS != ADCRC	CS = ADCRC
`1 1111 1111 1111`	8191 clocks of F_OSC	8191 clocks of ADCRC
`1 1111 1111 1110`	8190 clocks of F_OSC	8190 clocks of ADCRC
`1 1111 1111 1101`	8189 clocks of F_OSC	8189 clocks of ADCRC
...	...	...
`0 0000 0000 0010`	2 clocks of F_OSC	2 clocks of ADCRC
`0 0000 0000 0001`	1 clocks of F_OSC	1 clocks of ADCRC
`0 0000 0000 0000`	Not included in the data conversion cycle⁽¹⁾
Note: If ADPRE is not equal to ‘`0`’, then ACQ = `0` means Acquisition Time is 8192 clocks of F_OSC or ADCRC.

The individual bytes in this multibyte register can be accessed with the following register names:ADACQH: Accesses the high byte ADACQ[12:8]ADACQL: Accesses the low byte ADACQ[7:0]