2.6 Configuration Straps

Configuration straps allow various features of the device to be automatically configured to user defined values. They are identified by an underlined signal name in the pin assignment lists. Configuration straps do not have internal resistors to prevent the signal from floating when unconnected.

Important: The configuration straps are shared on pins with output signals. Pins identified as configuration straps must always be pulled high to VDDP or low to VSS through an external resistor.
Important: External pull-up or pull-down resistors must be sized appropriately (10 kΩ, typical) to ensure that the configuration straps reach the required voltage level prior to latching at reset. If a pull-up resistor is used, it must be connected to VDDP.

Configuration straps are latched on Power-On Reset (POR) and pin reset (RESET_N). At the completion of the reset, that is when all power supplies are above the thresholds and the RESET_N pin is no longer asserted, the associated register bit values are loaded.

Note: When a soft reset occurs via the Soft Reset bit of the Basic Control Register, the configuration of the device is determined by the contents stored in registers and is independent of the values of the configuration strap pins.

Device Mode (MODE[1:0])

The MODE[1:0] configuration straps determine whether the interface to the MAC is MII, RMII, or SC-MII, as shown in Table 2-13 below. The value can be read in the STRAP_CTRL0 register, if needed.

Note: As the LAN8672 only supports operation in MII mode, the MODE[1:0] configuration straps must be set to 01b.
Table 2-13. MODE[1:0] Configuration Straps
MODE[1:0]Definition
00bReserved
01bPHY is placed in MII mode with 25 MHz crystal
10bPHY is placed in RMII mode with 50 MHz REFCLKIN
11b

PHY is placed in Single Clock MII (SC-MII) mode with 25 MHz crystal. (LAN8670 only)

The TXCLK and TXER pins are used for other features. The RXCLK pin becomes a single MII clock output.

PHY Address (PHYAD[4:0])

During reset, the PHYAD[4:0] configuration straps are pulled high to VDDP or low to Ground through external resistors to give each PHY a unique SMI address. This address is latched into an internal register at the end of a hardware reset. In a multi-PHY application (such as a switch), the controller is able to manage each PHY via the unique address. Each PHY checks each management data frame for a matching address in the relevant bits. When a match is recognized, the PHY responds to that particular frame.

The LAN8670/2 SMI address must be configured using the PHYAD[4:0] hardware configuration straps to any value between 0x00 and 0x1F. The LAN8671 SMI address must be configured using the PHYAD[3:0] hardware configuration straps to any value between 0x00 and 0x0F.