The PIC18F24/25Q10 devices that you have received conform functionally to the current device data sheet (DS40001945E), except for the anomalies described in this document.
The silicon issues discussed in the following pages are for silicon revisions with the Device and Revision IDs listed in the table below.
The errata described in this document will be addressed in future revisions of the PIC18F24/25Q10 silicon.
Note: This document summarizes all silicon errata issues from
all revisions of silicon, previous as well as current.
| Part Number | Device ID | Revision ID | |
|---|---|---|---|
| A8 | B2 | ||
| PIC18F24Q10 | 0x71C0 | 0xA008 | 0xA082 |
| PIC18F25Q10 | 0x71A0 | 0xA008 | 0xA082 |
Important: Refer to the Device/Revision ID section in
the current “PIC18F2X/4XQ10 Memory Programming Specification” (DS40001874) for more
detailed information on Device Identification and Revision IDs for your specific device.
| Module | Feature | Item No. | Issue Summary | Affected Revisions | |
|---|---|---|---|---|---|
| A8 | B2 | ||||
| Electrical Specifications | Temperature Range | Industrial Temperature Range Only | Industrial Temperature Range Only | X | |
| I/O Ports | Ext MCLR | Internal Pull-up on MCLR Pin Enabled Late | Internal Pull-Up Enabled Late | X | X |
| Resets | LPBOR | Low-Power Brown-out Reset (LPBOR) Mode | Trip Point Rises with Temperature | X | |
| Resets | RMCLR Flag | The RMCLR Flag in the PCON0 Register Cleared by Mistake | POR may Clear the RMCLR bit by Mistake | X | X |
| Oscillator | HFINTOSC | Internal HFINTOSC Oscillator Varies up to 5% | 5% Variation Over Temperature Range | X | |
| Oscillator | XT Mode | Maximum Clock Frequency Limited to 2 MHz for XT Mode | Maximum Clock Frequency Limited to 2 MHz for XT Mode | X | |
| ADCC | FVR Reference | Missing Codes with FVR Reference | Missing Codes when FVR is Used as Reference | X | X |
| WWDT | Window Operation | Window Operation in Doze Mode | Window Feature of WWDT does not Operate Correctly in DOZE Mode | X | |
| NVM | NVMERR | NVMERR | The NVMERR bit is set by Device Reset after being Cleared by Software | X | |
| MSSP | SPI | MSSP SPI Client Mode | SSPBUF may be Corrupted by Writes to Other GPR/SFRs | X | |
| In-Circuit Debug | Software Breakpoints | Software Breakpoints Are Not Available | Software Breakpoints are not Available | X | X |
| PFM-Program Flash Memory | Self-Write | 1.10.1 | The First Instruction Following a Self-write Instruction may not Execute | X | X |
|
Note: Only those issues indicated in the last
column apply to the current silicon revision.
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