4.5.4.2.4 ULP2 Mode

The ULP2 Mode reset is entered when a WFE event occurs while CKGR_MOR.ULP2 is set to ‘1’ in the PMC.

When this reset occurs, only the Processor reset is asserted. The VDDCPU power supply can be switched off during ULP2 mode (refer to “ULP2 Mode” in the section “Power Management Controller (PMC)”.