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Up to 1-GHz Arm® Cortex®-A7, MIPI Camera, Dual Ethernet, Audio and Security
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Product Pages
SAMA7G54
Home
2
CPU and Interconnect
2.9
Boot Strategies
2.9.1
Standard Boot Strategy
2.9.1.5
Standard Monitor
2.9.1.5.3
USB Device Port
Introduction
Reference Document
1
Overview
2
CPU and Interconnect
2.1
Event System
2.2
System Interconnect and Security (SIS)
2.3
Cortex-A7 Processor (Arm)
2.4
External Interrupt Controller (EIC)
2.5
Debug and Test
2.6
NIC-400 Global Programmer’s View (NICGPV)
2.7
Bus Matrix (MATRIX)
2.8
DMA Controller (XDMAC)
2.9
Boot Strategies
2.9.1
Standard Boot Strategy
2.9.1.1
Overview
2.9.1.2
Flow Diagram
2.9.1.3
Chip Setup
2.9.1.4
Standard Boot Configuration
2.9.1.5
Standard Monitor
2.9.1.5.1
Command List
2.9.1.5.2
DBGU/UART Console Port
2.9.1.5.3
USB Device Port
2.9.1.5.3.1
Supported External Crystal/External Clocks
2.9.1.5.3.2
USB Class
2.9.1.5.3.3
Enumeration Process
2.9.1.5.3.4
Communication Endpoints
2.9.2
Secure Boot Strategy
2.9.3
Key Provisioning and Bootstrap Programming
3
Memories
4
System Controller
5
Analog Subsystem
6
Image Subsystem
7
Audio Subsystem
8
Security and Cryptography Subsystem
9
Connectivity Subsystem
10
USB Subsystem
11
Electrical and Mechanical Characteristics
12
Glossary
13
Revision History
Microchip Information
2.9.1.5.3 USB Device Port
