Jump to main content
Up to 1-GHz Arm® Cortex®-A7, MIPI Camera, Dual Ethernet, Audio and Security
Search
Product Pages
SAMA7G54
Home
9
Connectivity Subsystem
9.3
Flexible Serial Communication Controller (FLEXCOM)
9.3.7
USART Functional Description
9.3.7.11
USART FIFOs
Introduction
Reference Document
1
Overview
2
CPU and Interconnect
3
Memories
4
System Controller
5
Analog Subsystem
6
Image Subsystem
7
Audio Subsystem
8
Security and Cryptography Subsystem
9
Connectivity Subsystem
9.1
Overview
9.2
Gigabit
Ethernet MAC (GMAC)
9.3
Flexible Serial Communication Controller (FLEXCOM)
9.3.1
Description
9.3.2
Embedded Characteristics
9.3.3
Block Diagram
9.3.4
I/O Lines Description
9.3.5
Product Dependencies
9.3.6
Register Accesses
9.3.7
USART Functional Description
9.3.7.1
Baud Rate Generator
9.3.7.2
Receiver and Transmitter Control
9.3.7.3
Synchronous and Asynchronous Modes
9.3.7.4
ISO7816 Mode
9.3.7.5
IrDA Mode
9.3.7.6
RS485 Mode
9.3.7.7
USART Comparison Function on Received Character
9.3.7.8
USART Asynchronous and Partial Wakeup
9.3.7.9
LIN Mode
9.3.7.10
Test Modes
9.3.7.11
USART FIFOs
9.3.7.11.1
Overview
9.3.7.11.2
Sending Data with FIFO Enabled
9.3.7.11.3
Receiving Data with FIFO Enabled
9.3.7.11.4
Clearing/Flushing FIFOs
9.3.7.11.5
TXEMPTY, TXRDY and RXRDY Behavior
9.3.7.11.6
FIFO Single Data Access
9.3.7.11.7
FIFO Multiple Data Access
9.3.7.11.8
Transmit FIFO Lock
9.3.7.11.9
FIFO Overflow/Underflow Error
9.3.7.11.10
FIFO Thresholds
9.3.7.11.11
FIFO Flags
9.3.7.12
16-bit Data Protocol Support
9.3.7.13
USART Register Write Protection
9.3.8
SPI Functional Description
9.3.9
TWI Functional Description
9.3.10
Register Summary
9.4
Quad Serial Peripheral Interface (QSPI)
9.5
Secure Digital MultiMedia Card Controller (SDMMC)
9.6
Controller Area Network (MCAN)
9.7
Timer Counter (TC)
9.8
Pulse Width Modulation Controller (PWM)
10
USB Subsystem
11
Electrical and Mechanical Characteristics
12
Glossary
13
Revision History
Microchip Information
9.3.7.11 USART FIFOs
